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I have the circuit below.enter image description here Now my question is: why the rise time and fall time measured on Vout are the same as in a circuit using only one inverter gate?

I know the propagation delay is the sum of the delays, but can someone help me with a good explanation? Thank you!

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    \$\begingroup\$ What do you think the connection between propagation delay and output rise time could be? Could it be that there isn't one? \$\endgroup\$ – Andrew Morton Apr 2 at 13:45
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If you look at the unloaded rise time and fall time then it doesn't matter how many inverters you put in series. The rise time is the time it takes the output to rise from 10% of Vdd to 90% of Vdd, or between any two voltage levels you choose.

Now, the propagation delay is another matter entirely. Propagation delay is usually specified from the time when the input passes through 50% of Vdd until the output passes through 50% of Vdd. If you measure from Vin to Vout in your circuit, the propagation delay will be linearly proportional to the number of inverters (roughly).

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  • \$\begingroup\$ Thank you! I was thinking about that but wasn't sure if that is the correct answer or not :D \$\endgroup\$ – Shortcircuit Apr 2 at 15:00
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Clearly, your knowledge here about the propagation delay is sound, and it is the fault of the simulation designers or the settings for your simulation.
Depending on which software you use for simulations, there will be big gaps like the one here, or smaller and less obvious ones. In the end, your knowledge, understand, keen observation and real-world testing and measurements are the best assurance that your circuit works as intended or expected. Whichever software you use, I would not rely on it 100%.

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If the circuit's slew rate is limited by the FET's output current (as will be with all but light capacitive loads), then the Trise and Tfall are the same, whether 1 inverter or 3 or 5 or 7 etc inverters.

Note I've allowed the Trise to be different from Tfall, because of FET sizing imbalances.

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