Recently I was reading a Verilog study book. I finally realized that a Verilog file may not be synthesizable, because some Verilog statements are for simulation use only. But I'm too lazy to make one file to create a module and another to simulate it. Can I mix both up in the same file, and if so, how?

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    \$\begingroup\$ I like this question because I too am too lazy too make two files. How come the designers of the language didn't anticipate this? \$\endgroup\$ – dext0rb Nov 16 '12 at 6:22
  • \$\begingroup\$ Oh dear, I will be sad hearing this fact.Nevertheless, Is it a good hobit to put these file apart? @dextorb \$\endgroup\$ – LaiJiong Nov 16 '12 at 8:21
  • \$\begingroup\$ Yes, I believe best practice is to create both synthesis and simulation files for your modules. \$\endgroup\$ – dext0rb Nov 16 '12 at 13:38
  • \$\begingroup\$ Do you mean that you do not want to put your test bench in a separate file? You can always have two modules in a file and prevent one from being considered for synthesis with pragmas (or commenting it out...). What tool are you using? Many can generate test bench skeletons for you that take a lot of the busy work out of it. \$\endgroup\$ – Matthew Mellott Nov 30 '12 at 17:30

Most synthesis tools support pragmas. For example, in the following code, the and gate will not be considered for synthesis.

// synthesis translate_off
    and2 (a, b, c[4]);
// synthesis translate_on

Also, predefined macros can also be used:

`ifdef synthesis
 parameter PARAM = 4;

Both of the above are tool specific, so you'll have to see which predefined macros your tool supports, or you could define a macro yourself and use that.

If you'd like something more robust and not as tool specific, you can use a conditional generate statement that nicely splits simulation and synthesis:

if (SYNTHESIS == 1)
end generate

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