Recently I was reading a Verilog study book. I finally realized that a Verilog file may not be synthesizable, because some Verilog statements are for simulation use only. But I'm too lazy to make one file to create a module and another to simulate it. Can I mix both up in the same file, and if so, how?
Most synthesis tools support pragmas. For example, in the following code, the and gate will not be considered for synthesis.
// synthesis translate_off and2 (a, b, c); // synthesis translate_on
Also, predefined macros can also be used:
`ifdef synthesis parameter PARAM = 4; `endif
Both of the above are tool specific, so you'll have to see which predefined macros your tool supports, or you could define a macro yourself and use that.
If you'd like something more robust and not as tool specific, you can use a conditional generate statement that nicely splits simulation and synthesis:
generate if (SYNTHESIS == 1) ff_for_synthesis_here else ff_for_simulation_here end generate