I'm trying to understand how data is going to fill up a 64bit cacheline with x4 DDR4 DIMM. x4 DDR4 has 16 Banks, 4 Banks each in 4 Bank Groups and each bank is having 4 memory arrays. Burst size is 8.my understanding is column width is the no. of memory arrays within the Bank. Now my question is when i requested any data how is it fetched i mean whether all the 4 memory arrays provide 8 bits of data to fill the cacheline? how x4 relate with burst size 8?
The column width is the size of the Data Bus on the DRAM chip. Ex. reading from row 1, column 1 returns 'column width' bits. On DDR4 column width is 64 bits and the row size is 64 Kbits meaning that the row buffer contains 64 Kbits.
A cache line is typically 64 Bytes and not 64 bits. A burst size of 8 means that 8 data words are transmitted.
8 data words x 64 bits = 64 Bytes
that is the cache line size.