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See bottom of post for the actual questions

First, some context:

  • I'm making a DisplayPort switch as a hobby project
  • DisplayPort's high speed lines require 100Ω ± 10% differential impedance, which I'll be requesting impedance control from the fab
  • Off-the-shelf DisplayPort switch ICs are only available in 0.5mm pitch BGA (e.g., TI HD3SS214)
  • Ideally I want to support HBR3, which runs at 8.1Gbit/s (8b/10b encoded), or a fundamental frequency of 4.05GHz, so transmission line impedance matters
  • I can use FR-4 (εr = 4.2~4.4 @ 5GHz) or RO4350B (εr = 3.66) dielectrics
  • This is my first time working on a high speed design

So due to the 0.5mm pitch BGA limitation, the widest trace I can fit between the balls is 76.6µm (3.02mil). Fortunately, this just fits within the minimum trace width of 3mil on 1oz copper for the fab I've tentatively chosen (WellPCB).

But such thin traces present a problem in achieving 100Ω differential impedance (on a differential microstrip). My fab's standard 1st-to-2nd layer dielectric thickness on FR-4 is 213µm (7628H). Using the minimum trace spacing of 76.2µm (3mil) with the 76.6µm width, this results in Zdiff = 110~115Ω (according to MMTL), which is out of spec! Using the thinnest available RO4350B (168µm) is even worse with Zdiff = 117Ω due to the much lower εr.

While I can increase the trace width if I get around the balls with vias instead of routing between them (the bottom layer already contains other high speed traces), this would mean I would have to add an extra two layers to the PCB ($$$), and would be extra impedance mismatch.
Alternatively I can taper the traces to a larger width immediately after escaping the BGA, but this is annoying to do on my EDA software (KiCAD).

I could also try to ask the fab to use a custom FR-4 stackup, with a thinner upper layer, but I'm not sure how thin they can go.
I simulated the Zdiff on thinner FR-4 (see below image), and it seems 100µm would be ideal.

Simulated Z<sub>diff</sub>

I also worry that being right on the minimum 3mil trace width and spacing would mean the fab wouldn't be able to perform their own impedance control, since I heard it's primarily done by adjusting the trace width (can't go wider or won't fit between BGA balls; can't go narrower or it goes below the minimum 3mil).

Questions:

  • Should I be worried in using the minimum trace width and spacing of 3mil, when simulations show this results in a too high impedance? Will the fab be able to properly lower it?
  • If not, how would you recommend I break out the differential pairs?
  • Are my Zdiff simulations with MMTL accurate at all? I haven't been able to cross-check with other EM simulators, while simple online calculators have been giving me even higher values.
  • Have I made any stupid mistakes or incorrect assumptions? First time on a high speed design after all...
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    \$\begingroup\$ The problem you have is getting away from the chip. Once you escape the BGA, you can adjust the width/spacing to be within the 100 ohm tolerance, just remember to take into account the thinner traces when impedance/length matching. \$\endgroup\$
    – Ron Beyer
    Apr 3, 2020 at 21:22

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Neck-down traces are a common approach for this issue. If your PCB vendor can deal with the spacing and track width then this then it's a reasonable approach.

Otherwise I suggest using microvias to escape the traces to the bottom layer. Then you have more flexibility in trace width to achieve both Zo(diff) and Zo(single-ended), and the board will have better manufacturing yield.

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