Quick question here - are there any downsides to building a 3 input AND gate like this?
simulate this circuit – Schematic created using CircuitLab
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\$\begingroup\$ For one, '1' will be at least 2V below VCC because each transistor is used as an emitter follower, with Vbe=0.6 or 0.7V. And with only a 5K pulldown it won't interoperate well with traditional TTL whic requires sinking a certain current from a TTL input to maintain a clean logic '0'. \$\endgroup\$– user16324Apr 3, 2020 at 21:43
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\$\begingroup\$ So transistors will typically have a voltage drop across them like a diode? \$\endgroup\$– zvolk4Apr 3, 2020 at 21:45
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\$\begingroup\$ Uneven potential distribution? \$\endgroup\$– Marko BuršičApr 3, 2020 at 21:46
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\$\begingroup\$ Also npn transistor cannot transfer full high gate voltage as it requires Vbe drop to not cutoff \$\endgroup\$– acrossApr 3, 2020 at 21:47
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\$\begingroup\$ NAND and NOR are popular because they're universal gates. You can make any logic function using only NAND gates or using only NOR gates. You can't do that with using only AND gates. You want to use pnp transistors in parallel for NAND gate? \$\endgroup\$– acrossApr 3, 2020 at 21:51
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3 Answers
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simulate this circuit – Schematic created using CircuitLab
Figure 1. One simple test.
The circuit isn't very good.
- (a) With the bottom transistor on you'll get a potential divider between R3 and R4 of about 1/3 through the base-emitter junction of Q3 so Y1 would be about 5/3 V = 1.66. With the transistor B-E junction the simulation shows that the actual output voltage would be 1.44 V. This messes up your LOW signal.
- (b) With all three inputs pulled high you'll get Y2 = 4.13 V. Again this is a bit low for a HIGH.
The big problem with this is that your Y2 output can't drive another AND gate properly as the logic levels are deteriorating with each additional gate.
Figure 2. Another simple test.
- (c) Y1 -= 2.1 V. This is a terrible result as it's almost in the middle between an acceptable HIGH and LOW. This sinks any chance of it being a working gate.
- (d) Y2 = 0 V. At least this works.
answered Apr 3, 2020 at 21:49
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\$\begingroup\$ I suppose the Transistor himself knows a lot about logic gates.... thanks for the in-depth explanation! \$\endgroup\$– zvolk4Apr 3, 2020 at 21:51
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\$\begingroup\$ Would using two separate AND gates work better, or are NANDs better to use and just invert the output? \$\endgroup\$– zvolk4Apr 3, 2020 at 21:58
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\$\begingroup\$ Have a look at Discrete TTL NAND gate. NANDs are the simplest. AND gates are usually NAND followed by NOT. \$\endgroup\$ Apr 3, 2020 at 22:03
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\$\begingroup\$ Ok. I came across nandgame.com last night and it never crossed my mind until now that I can do everything I need with just NAND gates. \$\endgroup\$– zvolk4Apr 3, 2020 at 22:08
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3 X Inverter + NOR
(A' + B' + C')' = A'' * B'' * C'' = A * B * C
This circuit won't suffer the voltage drop issue, you can have many inputs.
simulate this circuit – Schematic created using CircuitLab
answered Apr 3, 2020 at 22:08
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In this method the output does not suffer voltage loss
