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It seems like a master-slave flipflop always has around a 2-gate delay between the Master and Slave sections of the flip flop. For example:

enter image description here

My question is what would happen if, theoretically, there was a zero-delay between the Master and Slave sections of the flip flop? Would the master/slave relationship still work properly, or is it dependent on there being a delay between the Master and Slave sections of the flip flop?

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  • \$\begingroup\$ if the gate delay in the Master D flip-flop is longer than the Clk hold time plus Clk inverter delay, then there would be a problem \$\endgroup\$
    – jsotola
    Commented Apr 4, 2020 at 18:00

2 Answers 2

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For the circuit you show there are no race conditions...no dependencies on certain delay values...as long as you satisfy a setup and hold requirement for the D input with respect to the clock. In other words, as long as the D input doesn't change at the same time as the clock then the flip-flop will function correctly without gate delays.

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The two latches are activated at different times, separated by half of a clock. (You will notice that the flop is negative edge triggered.)

As long as the first latch setup / hold time is met, its output is guaranteed to be stable when its contents get transferred to the second latch. So even if the first latch has zero delay its output will not change while the second latch is open.

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