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I've built a JK master-slave flip flop according to the following schematic:

enter image description here

Putting it into Logicly I have the following diagram:

enter image description here

However, regardless of which switches I change, the final two NOR gates's outputs never changes. Here's a video showing this: https://gyazo.com/a8982643c436c6b7084d9a3eca577f13 (with a working gated SR latch above).

Is there a certain properly of this circuit that the circuit-simulator isn't taking into account? Or is the schematic I've created incorrect? I thought creating the master-slave relationship would correct the previous JK-latch error I had.

Additionally, simulating D flipflop seems fine, so curious why the feedback in the JK might be so different.

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  • \$\begingroup\$ the input switches are suspect ... use SPDT switches ... connect NO to HIGh ... connect NC to LOW .... connect C to input \$\endgroup\$
    – jsotola
    Apr 4, 2020 at 22:11
  • \$\begingroup\$ @jsotola could you please view the updated video? I've shown one circuit that works with that orientation. Do you think I should still change them? gyazo.com/a8982643c436c6b7084d9a3eca577f13 \$\endgroup\$
    – David542
    Apr 4, 2020 at 22:13
  • \$\begingroup\$ compare your circuit to the one in your previous question ... electronics.stackexchange.com/questions/491003/… ... they are not the same ... i am not talking about the conversion from NAND to NOR per se ... i am saying that the conversion was done incorrectly \$\endgroup\$
    – jsotola
    Apr 4, 2020 at 22:43
  • \$\begingroup\$ @jsotola which part of the above is incorrect? The schematic I took from another source. \$\endgroup\$
    – David542
    Apr 4, 2020 at 23:21
  • \$\begingroup\$ where did you get the schematic? ... a NAND gate is equivalent to an inverted input OR gate \$\endgroup\$
    – jsotola
    Apr 4, 2020 at 23:47

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