0
\$\begingroup\$

I am going through this TI-APP note - Voltage Supervisor,with hysteresis.

I am not able to understand WHY they have derived the below equation 1 & equation 2 in the App note (page 2 & page 3)

I understand that the equation is obtained by using the KCL at the nodes.

My questions :

  1. Why should I apply KCL there?

  2. How is performing KCL there linked to finding the voltage at which RESET pin will change its state?

Please explain

enter image description here

enter image description here

\$\endgroup\$
  • \$\begingroup\$ Q1 - Personal preference but most EE prefer nodal analysis over the mesh. Q2 - the "switching" will occur when Vs = V_threshold. \$\endgroup\$ – G36 Apr 5 at 9:47
  • \$\begingroup\$ Yes. But the threshold voltage is not included in the calculation. And Why does the RESET voltage state change when the current is in this condition (based on Equation 1)? This is what I am not understanding. Suppose, the current through R1 is like 3mA. And based on some value of resistance, the current through R2 and Rh, may split as 2mA & 1mA or vice versa or any other combination. What relation does this have with the voltage ? Please help me with an answer \$\endgroup\$ – Newbie Apr 5 at 10:20
  • \$\begingroup\$ I don't know why they have gone to this; Vs is set by a simple voltage divider that only differs from when Vout is low or high. \$\endgroup\$ – Peter Smith Apr 5 at 10:54
1
\$\begingroup\$

In this example, the Ti engineer is using Nodal analysis at \$V_S\$ node.

Nodal analysis is used to find the voltage at a given node, and this method is base on KCL and some "mathematic magic".

But we can use any network analysis technique we know or like/prefer.

We have two cases.

1 - Input voltage increases

$$V_{S+} = V_{1+} \times \frac{R_2||R_{TH}}{R_2||R_{TH} + R_1} = V_{1+} \times\frac{\frac{R_2 R_{TH}}{R_2 + R_{TH}}}{\frac{R_2 R_{TH}}{R_2 + R_{TH}} + R_1}$$

2 - Input voltage decreases

$$V_{S-} = V_{1-} \times \frac{R_2||(R_{TH}+R_P)}{R_2||(R_{TH}+R_P) + R_1} +V_2 \times \frac{R_1||R_2}{R_1||R_2 + (R_{TH} + R_P)} $$

As you can see I used a voltage divider equation and superposition theorem.

Why is the voltage divider formula used in this circuit to find the terminal voltage?

Now in the example, we have

\$V_{1+} = 2V\$

\$V_{1-} = 1.8V\$

\$V_{2} = 1.8V\$

\$V_{S-} = 0.4V\$

\$V_{S+} = 0.406V\$

\$R_{TH} = 1M\Omega\$

\$R_P = 100k\Omega\$

So, we have two equations and two unknowns thus we can solve for \$R_1\$ and \$R_2\$.

click here for the solution in kiloohms

enter image description here

And how a comparator with hysteresis work you can read here: Waveform at the negative terminal of an OPAMP

What is the purpose of a resistor in parallel with a buffer gate?

| improve this answer | |
\$\endgroup\$
1
\$\begingroup\$

Take a look at Figure 1 in the link you gave. It explains that the reset output has a pull-up Rp to voltage V2 and reset output is fed back to VS+ via resistor Rh. The reset output is clearly open-drain output so either reset is pulled to 0V by the chip, or it floats to V2 via Rp. That is why VS+ is pulled down to 0V only via Rh, and pulled up to V2 via Rh and Rp.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ Yes, I get that connection. but it is the KCL which they have applied I am not getting. In figure 2, By their equation, they are saying that the current going through R1, is equal to the sum of currents going through R2 and Rh. So, why does the RESET voltage state change when the current is in this condition? This is what I am not understanding. \$\endgroup\$ – Newbie Apr 5 at 10:17
  • 1
    \$\begingroup\$ In figure 2 the supply voltage is rising so reset will be low, that is why Rh is grounded an thus pulls extra current from Vs+ node so Vs+ is lower than simply with R1 and R2. When supply rises to high enough that Vs+ equals Vt, the reset changes state to high, so via Rh and Rp extra current is pushed into Vs node so it is at higher voltage than it would with simply R1 and R2. Thus figure 3 is that situation, again when supply falls, it must fall low enough for Vs+ to match Vt which is the point where reset goes low again and Vs+ jumps down because of Rh. \$\endgroup\$ – Justme Apr 5 at 11:20
  • \$\begingroup\$ Thank you for this comment. Got it. Could you please edit this comment with some example numericals? \$\endgroup\$ – Newbie Apr 5 at 11:42
  • \$\begingroup\$ No, because comments can only be edited for 5 minutes, and you already have the numerical example for calculations in the application note. \$\endgroup\$ – Justme Apr 5 at 11:47

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.