I've synthesized a design for a Coolrunner II CPLD. I intend to use the CPLD's internal clock. I have an input named CLK. I look at the fitter report and I see this:
** Global Control Resources ** GCK GSR GTS DGE Used/Tot Used/Tot Used/Tot Used/Tot 1/3 0/1 0/4 0/0 Signal 'CLK' mapped onto global clock net GCK0. ** 16 Inputs ** Signal Bank Loc Pin Pin Pin I/O I/O Name No. Type Use STD (snip) CLK 1 FB2_7 43 GCK/I/O GCK LVCMOS18 KPR
Of course, CLK is indeed the name of the input I'd like mapped to the clock. But how did it know to do this?
One 'gimme' is that CLK is a standard name and XST made a good guess. So I renamed every CLK signal in the design to 'XXX'.
I re-synthesized (?) and now the report says:
Signal 'XXX' mapped onto global clock net GCK0.
So what gives here. How is this working?
All that being accepted, will XXX now be the hardware clock, or is there some other step I must take?
EDIT: where XXX is used.
always@(posedge foo) //create 1 and 2 pipe delays of inputs begin aq2 <= aq1; aq1 <= aquad; bq2 <= bq1; bq1 <= bquad; end
This is in a quadrature decoding module. XXX is passed as an argument. foo is XXX here. Of course, this is just Verilog, I don't know what it's doing under the hood.
Edit 2 - enlightenment has occurred.
I have misunderstood what GCK is. I thought it was a clock signal generated by and internal to the CPLD. It is not. The GC stands for 'Global Control'. It's an architectural mechanism that allows a signal to be propagated around the CPLD's macrocells at very low cost and low skew. It's a network, not a clock. The CoolRunner II does not have an internal clock. I will have to conjure a clock and connect it to pin #43 (the GCK pin) of my xc2c64a CPLD.