# Does ground pour circumvent bypass capacitors?

I am working on a two-layer PCB with ground pour in both layers. A few of the components recommend using bypass capacitors.

Going off of this guide, I understand that it is important that the current passes through VCC and GND directly through the capacitor.

The route seems to correctly pass through the bypass capacitor before I add the pour.

However, after I add the pour, now the current can circumvent the bypass capacitor. Does this make the bypass capacitor ineffective? Do I have to remove the ground pour from the VCC and GND pins when using bypass capacitors?

• Please watch this video. It allows you to clearly visualize the effect of bypass capacitor placement, and the fact that whether current "hits" the capacitor first or last is entirely unimportant: youtube.com/watch?v=1xicZF9glH0 – DerStrom8 Apr 8 at 1:00
• It would be helpful to see enough of the rest of the board to see where the C8 leads are going. Is the IC just off the page, or is it 15cm away somewhere on the other side of the board? It would also be helpful to know what the IC is, what else is on the board, what environment it will be working in, what frequencies will be present on the board, whether you have any transmitters, etc, etc. Designing a board is specific to the system - if you're looking to break general rules then you need to guarantee that your specific system can safely exempt itself from those rules. – J... Apr 8 at 15:26
• @J... The chip that it is decoupling is just to the left of the capacitor. – Ron Beyer Apr 8 at 15:38
• @RonBeyer Right - missed that. Still don't know what IC it is or what else is on the board. I'd definitely break the ground line running under the IC. The pour can go there but it shouldn't bond to pin 2. The pour should also not touch the trace between pad 2 of the IC and the cap. – J... Apr 8 at 15:44
• Components can't make recommendations. Where does the recommendation come from? Respond by editing your answer, not here in comments. Thanks in advance. – Peter Mortensen Apr 9 at 0:24

Your instructional diagram diagram is bogus for the most part (or at least, leaves certain rather important practical things unsaid). There's nothing wrong with A, B, C, or D (as long as D has a ground plane), at least until you get into the frequencies where everything is an antenna or transmission line. Adhering strictly to F and making concessions to do so can get you worse results until this point.

Going off of this guide, I understand that it is important that the current passes through VCC and GND directly through the capacitor.

No. Do not think of bypass capacitors as a warehouse where a truck carrying currents stop along the way to unload some of its cargo.

Think of bypass capacitors as operating on an AC high frequency circuit where the capacitor is the source superimposed on a DC circuit where the power supply is the source.

As long as you aren't at the point where everything is a transmission line or antenna, your objective is to minimize the distance/loop area/ inductance between the pin and the capacitor. That's all. Strictly making traces drop off at the cap before the pin at the expense of short traces and small loop areas just makes things worse until things like antenna stubs come into play.

For example, if a cap is under an IC, don't run traces from the plane to the cap then to the pin. Yes, it adheres to F but it also makes the trace length and loop area larger which makes things worse if you are not in the frequency range where antenna and transmission line effects matter. At those frequencies, everything you do matters including trace width, shape, the way corners bend, and PCB material characteristics.

From Electromagnetic Compatibility 2009 by Henry Ott:

• @sgt_johnny No, it doesn't work like that. You would only come to that conclusion if you were using mechanical analogies. I get it, I initially thought this way too until I looked into it. But as I already said, this is not like a truck making multiple stops at warehouses along the way to the city. But this is more akin to AC and DC superposition. Real life example: The very highest frequency processors are on BGAs and therefore would be the most sensitive to this kind of issue. Tell me how a BGA can physically arrange things like this? Answer: It can't. – DKNguyen Apr 7 at 18:28
• @sgt_johnny But what you just said supports what I said: It ISN'T important that the trace must go to the cap before going to the via. What's important is minimizing the loop inductance. If the cap is under the BGA, are you going to run traces/vias from the plane to the cap, then run traces/vias from the cap back through the board to the pin? Of course not. That just makes things worse. You're going to run vias from the plane to the pin, and from the plane to the cap. – DKNguyen Apr 7 at 18:45
• just to be picky: electromagnetic waves have a propagation velocity. If keeping that in mind, this guideline makes sense. But this es exremely picky... in particular for µCs... – yar Apr 8 at 12:28
• This answer makes assumptions that are not necessarily true. A->F can have very large differences, depending on the frequency range the circuit is operating at. It's absolutely true that the cap cannot filter properly if you attach antennas going off in all directions - it's stuck, then, at the rear end of the transmission line doing absolutely nothing. Especially if you've got GHz transmitters on the same board this answer is very much oversimplified. Your objective is to minmize the distance/loop area/ inductance between the pin and the capacitor. That's all. - NO, this is wrong. – J... Apr 8 at 14:00
• @J... I'll admit when you get into RF and antennas things get real picky. However, this post pertains to decoupling and the OP's diagram implies prioritizing stopiing off at the cap before the pin to such an extent that one should increasw trace length to take detours to stop by capacitors before connecting to pins, which makes things worse in the vast majority of cases. – DKNguyen Apr 8 at 14:15

The various paths are all exploited by the electrons, proportional to susceptance.

Susceptance is the inverse of the vector-sum of resistance and reactance.

Highly inductive paths (large loop area is major variable) have high reactance and thus low susceptance, thus fewer electrons take those paths.

Ultimately the combination of all paths, the susceptance of each path, and the electrons using each path, will minimize the energy wasted.

If you need to reject the most noise, follow the rules. Don't bond the ground pin to the pour under the chip. That plane is acting as a faraday shield - you don't want it polluting your digital reference level. Same with the lead coming from the capacitor - waves on the ground plane can also bypass the capacitor - break that bond there also.

On the 3V3 lead, don't daisy-chain from pin 1 on the IC - I'd back that up to pad 1 on C8.

We don't really know what IC you're using or what types of noise you anticipate needing to reject. If RF or microwave interference is anticipated and problematic then sticking to the design rules is probably a good idea.

It looks like you are using Autodesk Eagle according to the pictures. In this case, yes you have to remove the pour around the capacitor. This usually can be done by placing a line with a width of zero on the Keepout Layers.

If you are using thermal reliefs, like on the picture, this is very easy, you just can place a line on the thermals you don't want

• This is entirely wrong, the connection to the pour is much more preferable. The inductance of the connection is drastically reduced. – DerStrom8 Apr 8 at 1:04