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I am making a project of noise cancellation using least mean sqaure algorithms through microcontroller. In that I need two signals to implement LMS algorithm i.e noisy and noise+clean. So my question is how can i sample these signals simultaneously? Is there any way to sample both signals at the same time?

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    \$\begingroup\$ What is the model of your AVR μc? \$\endgroup\$ Nov 18, 2012 at 13:34
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    \$\begingroup\$ Realistically, an AVR is not a good choice for an audio DSP application. Consider using either a DSP chip, or at least a higher performance general purpose micro (ARM, etc). \$\endgroup\$ Jan 18, 2013 at 17:10

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Tell us more about your signals. If they're slow enough, you may be able to get away with using on the onboard ADC. You didn't say which AVR model you're using, but most AVRs I've used had a maximum sampling frequency of around 4kHz. If you need to sample two signals with it, the ADC is multiplexed, so cut that in half. Unless your signals are significantly slower than that (and without trying it, I would guess a factor of 10 would be pushing it), I would go with a two-channel external ADC. The goal is to sample fast enough that relative to the slower signal, the samples were taken at approximately the same time. The multiplexer in the onboard and some external ADCs will take some finite time to switch. This needs to be considered. The uC clock also needs to be running fast enough that it can complete the necessary math before the next samples.

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The AVR XMEGA-A series can sample several signals in parallel. Read AVR1300 for more information. From my understanding you can sample 2 values with only 1 ADC clock cycle delay, which isn't simultaneously but close. THis is as far as i know the best you can get from the AVR series.

From AVR1300: " [...] Each signal propagates through the pipeline, where one bit is converted at each stage. In this way the ADC in the XMEGA A is capable of sampling one signal every ADC clock cycle, even if each signal must propagate through all stages in the pipeline before the result is ready in the result register. The propagation time for one single signal conversion through the pipeline is 7 ADC clock cycles for 12-bit conversions and 5 cycles for 8-bit conversions. [...] At full utilization the XMEGA A ADC delivers one result every ADC clock cycle [...]"

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    \$\begingroup\$ It should be noted that the ATXmega and ATmega are different microcontroller series. \$\endgroup\$ Feb 17, 2013 at 14:25
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If you really need the samples to be taken at the very same time (you don't) a number of microchip dspic have 2 internal independant ADs. Use their parametric search tool to find them. Or, use an external ADC.

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    \$\begingroup\$ If you think the OP doesn't really need simutaneous sampling, you should explain why. \$\endgroup\$
    – Dave Tweed
    Nov 18, 2012 at 12:40
  • \$\begingroup\$ Actually some dsPICs have two internal A/Ds whether he really needs the samples to be taken at the same time or not. \$\endgroup\$ Nov 18, 2012 at 20:11
  • \$\begingroup\$ @Dave Tweed - the lack of a need for truly simultaneous sampling should be obvious given that this is an audio application. What the actual skew tolerance between channels is depends on a number of unstated factors, but it is clearly not zero. \$\endgroup\$ Dec 19, 2012 at 16:27
  • \$\begingroup\$ @ChrisStratton: You're a bit late to this conversation, but I don't agree that all audio applications are not sensitive to skew. I once worked on an audio project where inter-channel timing had to be controlled to within 1 us. Now, while this does not necessarily require simultaneous sampling, given what the OP is trying to do, I can believe that his algorithm is predicated on simultaneous sampling. This is why I asked this answerer to explain his assertion. \$\endgroup\$
    – Dave Tweed
    Dec 19, 2012 at 17:05
  • \$\begingroup\$ Please explain what the alleged consequence of 2uS skew would have been in the application you mention. \$\endgroup\$ Dec 19, 2012 at 17:20

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