enter image description here

I'm having trouble answering this question, it is for my laboratory. My online lab sessions only discussed how to answer it briefly.

I am not sure how to go from here, I've filled in the K-map with ones and don't cares just so 1-6 numbers are valid but I am not sure how to make the schematic for this?

  • \$\begingroup\$ The "Paste optional Schematic from ISE " suggest this has to be done using the Xilinx HDL tools. Is this supposed to be written in verilog/VHDL? \$\endgroup\$
    – Oldfart
    Apr 8, 2020 at 6:39

1 Answer 1


So you need to detect a 6, and on the next clock edge cause a preset to 0001.

  • 3
    \$\begingroup\$ This is a sketchy, undetailed comment but posted as an answer. \$\endgroup\$
    – TonyM
    Apr 8, 2020 at 6:49

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.