I have a CPLD connected to a BUS and an EEPROM. The bus has 3v logic and is 5v tolerant. The CPLD is 3v only.

If I configure the CPLD pin to be in the high-z state and the eeprom drives that pin to 5v would that damage the CPLD even though its now "floating"? The eeprom/cpld are connected in parallel to the bus.

Sorry if this seems like an obvious thing - I'm quite new to all this :).

  • 1
    \$\begingroup\$ What does the datasheet say? \$\endgroup\$ Commented Apr 8, 2020 at 21:41
  • \$\begingroup\$ maybe you should specify part numbers, that allows for the community to give you accurate and explained answers \$\endgroup\$
    – diegogmx
    Commented Apr 8, 2020 at 23:46

1 Answer 1


It could cause damage. There are still transistors (both for output and input) behind that CPLD pin even if they are not conducting. Think about it. Can a transistor that is blocking block an arbitrarily high voltage? No.

I would not assume a pin that outputs 3V would be able to block anything more than 3V, but you can check your CPLD electrical characteristics in the datasheet to verify.

Also, even if the transistor itself might be able to block 3V it is likely never going to get the chance unless things go really bad and the internal ESD diodes blow. Digital pins almost always have clamp diodes with a forward voltage drop of \$V_f\$ for ESD protection. If the line gets higher than \$V_{dd} + V_f\$ or lower than \$GND - V_f\$, then a diode will forward bias and conduct from the pin to the corresponding power rail.

If you apply a voltage higher than the supply voltage of the chip, or lower than the GND of the chip, these diodes will forward bias and conduct. Via this route, you could be applying 5V directly to the power pins of the chip itself (or your driver chip will be fighting the power supply which isn't good either), not just the blocking transistors behind the pin.

This is why its bad to drive unpowered chips. You can inadvertenly power up the chip partially through its signal pins.


simulate this circuit – Schematic created using CircuitLab

What this does mean, however, is that you could add a series resistor to limit the current flowing through these diodes and provide something else to drop the extra voltage across. This will, however, slow down your line speed. You can also add external diodes for more power handling. This is a method commonly used to clamp the voltage of a line.

  • \$\begingroup\$ intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/… Is page 5–6 Chapter 5: DC and Switching Characteristics what I should be looking at? Which says the max high logic level voltage is 4? \$\endgroup\$
    – paulm
    Commented Apr 8, 2020 at 21:52
  • 1
    \$\begingroup\$ @paulm Yes, Table 5-2 \$\endgroup\$
    – DKNguyen
    Commented Apr 8, 2020 at 21:54
  • 1
    \$\begingroup\$ @paulm See also page 54, table 2-7, note 5 of that datasheet. They can be 5V tolerant, but only with an external series resistor. \$\endgroup\$ Commented Apr 8, 2020 at 22:52

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.