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I am trying to find a way to load/execute code that is stored on an external SRAM chip without having to load it to the microcontroller internal memory. I'm not 100% sure of the name for what I'm trying to do but I think a memory mapping would work.

Reading the CMSIS driver for the board, this file (large file so no line numbers, but search for "#define APB1PERIPH_BASE" ) shows me that the peripherals of the boards, buses and such are already handled with memory mappings. So with this, I was thinking of mapping a region of code with an interrupt that would fire on memory accesses so I could fetch the data from the device using the SPI bus of my project's board. Doesn't need to be fast.

I thought also of using DMA but I'm similarly stumped.

I can't seem to find any definitive documentation either on creating a memory map or handling DMA with Peripheral->Device and Device->Peripheral transfers. I have a bunch of documentation on DMA internals but nothing with concrete information regarding memory maps.

I'm assuming that the STM32Cube CMSIS library has specific initialization code to setup the existing memory maps for the board but it must be using a precompiled driver because I can't see the source files, only headers.

I'm otherwise lost in the vastness of the ARM documentation and it is taking a long time to skim the documentation since I can't exactly name the thing I need in the same terms as in the documentation.

To keep it in simple terms, how can I create a memory map for an STM board using the STM32CubeF7 so I can transfer information to and from an external chip without loading/storing parts of the data in the main microcontroller memory.

Code examples would be great but I'm also looking for documentation for how it works in details.

EDIT 1 :

I have begun reading in more details the ARM Cortex M7 - Generic User Guide (page 28), and it in they mention a range of memory used for External RAM. What I am really looking for is how to wire up external RAM on my board to be used as external RAM.

ARM M7 Generic User Guide

I will keep analyzing the document but I have not seen specific documentation on using external SRAM chips as an ARM external RAM.

EDIT 2 :

I have found several questions on StackOverflow regarding programming STM boards with external memory chips. One of them was using FMC and it linked to a document by STM. Now I think I understand better what the current situation is and what the answers and comments on this question were saying.

Since I am using SPI right now, it would be impossible to map this directly to memory. Instead there are protocols like FMC and QuadSPI (or QSPI?) where the protocol and external chip specs can function with memory mapping. The linked document above (AN4761) shows examples on how to setup such functionality using SRAM, NAND and other chip types.

Reference material :

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    \$\begingroup\$ I think you can only do this with the FMC which means it has to be parallel. Or QuadSPI if it is available. \$\endgroup\$
    – DKNguyen
    Apr 9, 2020 at 1:58
  • \$\begingroup\$ Okay, I don't know yet what is FMC. I will investigate. \$\endgroup\$
    – Tristan Dubé
    Apr 9, 2020 at 2:06
  • \$\begingroup\$ Do you have a particular type of external memory in mind? If it's a parallel interface then the FMC could probably be configured to access it or if it's a SPI device, then the QuadSPI module could probably do it, as DKNguyen has suggested. Either FMC or QuadSPI can be mapped into a memory block, and you should then be able to execute code by jumping to an address in that block. You'll need to make sure though that the code is compiled to be executed in that block of memory addresses. \$\endgroup\$
    – brhans
    Apr 9, 2020 at 2:25
  • \$\begingroup\$ Right now I have SPI devices so I'm leaning toward QSPI but I don't know anything about it. I started reading the driver source github.com/STMicroelectronics/STM32CubeF7/blob/master/Drivers/… and I see a few mentions of memory mapping. Given this, if something works with QSPI using memory mapping, theoretically it could work with any other technology right ? Unless there is some specific wiring done on the bus to allow QSPI to work. \$\endgroup\$
    – Tristan Dubé
    Apr 9, 2020 at 2:31
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    \$\begingroup\$ No, QuadSPI and FMC are expecting hard-baked protocols to function. That's why they can work memory mapped. \$\endgroup\$
    – DKNguyen
    Apr 9, 2020 at 2:34

2 Answers 2

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The only peripherals that have memory mapped external buses are FMC and QSPI, so execution is only supported from external memory types that those two peripherals support. But you can't boot from them, so you need a program (bootloader) that initializes the necessary peripherals and jumps to execute from FMC/QSPI address you want.

All other types of external storage (SPI, I2C, SD card etc) needs the contents to be loaded to memory that supports execution (on external FMC/QSPI bus or internal RAM/Flash). There is no way to change how the memory is mapped.

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  • \$\begingroup\$ Ah ok, that is insightful. I wasn't aware of the specific buses needed for execution. Is there anyway to use other buses for just reading/writing to device memory using a mapping (not executing) ? \$\endgroup\$
    – Tristan Dubé
    Apr 9, 2020 at 17:21
  • \$\begingroup\$ I guess it reads in the MCU manuals. I still don't understand what you mean by mapping, but of course the other peripherals can be used to read and write data to/from external devices to internal memory - that's what they are for. \$\endgroup\$
    – Justme
    Apr 9, 2020 at 17:24
  • \$\begingroup\$ Sorry, I guess my background is more towards OS and systems programming and not much towards electronic systems. Im plain terms this is what I'm taking about en.wikipedia.org/wiki/Memory-mapped_I/O it might seem obvious since all IO is done with memory mapped ranges. Using a mapped range corresponding to the SRAM chip prevents me from having to load from SRAM over to MCU memory and then from MCU memory to cpu registers. Hopefully this makes more sense. \$\endgroup\$
    – Tristan Dubé
    Apr 9, 2020 at 17:30
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    \$\begingroup\$ The memory map is already fixed - all peripherals sit on the memory bus, just like Flash or SRAM. It's just that for example UART and SPI peripherals might take only few addresses, but for FSMC and QSPI, they already take 2 gigabytes in the address map to route memory accesses to external memory devices with the configured protocol - parallel memory bus or QSPI bus. Other peripherals can't do that. \$\endgroup\$
    – Justme
    Apr 9, 2020 at 17:43
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In order to execute from a memory it has to be connected to instruction bus of the ARM processor.
The Cortex M7 is a bit more complicated than an M4, but the matrix diagram still holds.

enter image description here

The bottom of the ARM Cortex M7 up left is the AXIM bus where instruction are fetched. In order for that to work there has to be a connection to the RAM or FLASH.
The flash and ITCM are wired up with the thick bus (64 bit).

The 32 bit is wired up trough the AXI-AHB matrix, and only SRAM1, SRAM2, FMC and Quad-SPI offer a connection for the AXIM bus this way.

The connection to all other peripherals is trough the AHBP or AHBS and there instruction fetches are not possible.

Resources:
STM32 Reference Manual
STM32 datasheet
Cortex M7 technical reference manual

And the reason you can't use normal SPI or I2C for instructions is very simple:
There is no hardware to translate the bus sequences to spi/i2c sequences. FMC and QSPI do have this, and those also have a memory region to map external memory to.

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  • \$\begingroup\$ Thank you for the diagram, I haven't managed to find it in my documents but I was looking for it. I'll browse your resources and see if this will fit my needs. As an aside, you said specifically for executing data only QSPI and FMC would work. Is there a way for other simpler protocols such as SPI to not execute but only refer to the data ? I'm thinking specifically of mapping a range of memory to SPI and load/store from it from C code ? \$\endgroup\$
    – Tristan Dubé
    Apr 9, 2020 at 17:17

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