If you apply a positive Vgs value to a P-Channel MOSFET, will the Rds be a high impedance value (assuming that Vgs is within the MOSFET rated spec), or would applying a positive Vgs damage the MOSFET?
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\$\begingroup\$ If you look at datasheets they will specify a +/- number for maximum tolerable Vgs, for both NMOS and PMOS. \$\endgroup\$– DKNguyenApr 9, 2020 at 23:04
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2 Answers
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If the voltage is within Vgs rating it will not damage the P-channel MOSFET and the MOSFET will remain off.
Just the mirror image of applying a negative Vgs to an N-channel MOSFET.
answered Apr 9, 2020 at 22:56
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Think about the C-V curves! It has to be part of any university curriculum.
A positive Vgs for PMOS devices is the same as a negative one for NMOS devices. In this case the usually major type of charge carrier are repelled from the gate, and unless the device is using an SOI process, the originally minor carriers will accumulate in the channel. So the devices COULD act as a transistor, though with much worse channel resistance. That's why the C-V curve look a bit symmetrical. As long as the voltage does not exceed the gate oxide breakdown, the process is reversible, without any remaining damage.
