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I am designing a PCB which reads analog signals via some ADC, my circuit looks like this:

enter image description here

enter image description here

There are four of those in a single board. My top copper is filled with a power plane (3V3) and bottom copper is filled with a ground plane. The components under the pad 1, 2, 4 of A1 or A2 are the plug detect components, and components near pads 3 and 5 are the filters.

I have learned that the ground of the analog components should be separated from the ground of the digital IC components.

My questions are:

  • If I make another plane for the analog ground how would I connect them to the digital digital ground? Should I use some ferrite? And what values?
  • How big should the distance be between the analog and digital ground?
  • Am I overthinking things? the frequency of the signal that will pass there is only max 70Hz.

I already have a prototype and it works great, but because there are some minor adjustments, the opportunity is there to improve the design. I would like to respect good design practices.

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    \$\begingroup\$ I (and many others I know) have made a living from fixing separate planes. Shape the planes instead. I separate the power (via filtering) but never the return. There are a lot of answers on this subject including one of mine. electronics.stackexchange.com/questions/185306/… \$\endgroup\$ – Peter Smith Apr 10 at 13:04
  • \$\begingroup\$ @PeterSmith shaping seems to be the common answer for articles, separating the ground planes is also be called shaping since they will be connected back to each other somewhere. I apologies it seems to be a lot to take in for me yet. You mention of "make the return currents flow where you want them to go" which of the devices would i particullary look this out for ? the Analog components or the digital components? I assume the digital components is the one responsible for making the noise and messing up the analog signal correcT? \$\endgroup\$ – Jake quin Apr 10 at 13:27
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If i make another plane for the analog ground how would i connect them to the digital digital ground? Should i use some ferrite? and what values?

It's all there in the data sheet for the ADS1115 (the ADC you are using): -

enter image description here

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$ – Voltage Spike Jun 3 at 15:04
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if you use full-coverage planes, the charges will go everywhere proportional to susceptance. All paths will be exploited, some paths used more than others. But ALL paths will be exploited because that minimizes the energy.

Thus if you expect extreme dynamic range in the ADC, you need to plan the paths of charges.

Local batteries are one way to keep most of the spikes and trash to be local to the circuit demanding the sudden surges of charge; a LOCAL BATTERY is a shunting capactor and a series resistor or inductor; this series/shunt is just a low-pass-filter installed in the VDD path. You must attach the GND end of the capacitor to the GND node in the spike-generating circuit.

I've used this Local Battery concept to implement (first pass successful) a 4-gain-block amplifier of Av = 600,000 for a magnetic beacon detector. The gain distribution was 20X (low noise amplifier), 1/2/4/8 (selectable to fine tune the ADC loading), 8/64 and 8/64 (for gross adjustments of gain, as distances changed). Gain was 26dB LNA + 5 * 18 or 90dB === 116dB total. Lots of twisted pairs were used from sensor, and to ADC, to minimize those magnetic fields. And nearby black-brick switch-regs were bad. Passband was 50KHz to 300KH with many poles and zeros to craft the response.

Other ways to guide spikes and trash are ----- slits in planes.

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  • \$\begingroup\$ Unfortunaly i cannot accomodate battery( chemical reaction battery, im not sure if you ment this) to my design. Can you check my proposed new PCB layout that utilizes slits in planes from which i was influence by your answer to this question. \$\endgroup\$ – Jake quin Apr 12 at 13:29
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Generally, these splits of GND planes are made as a function of frequency. As your sampling speed on the ADC goes up, you can see harmonics between the power supply feed-through from the digital and the analog sampling clocks. You can overdo this however, I have seen people arbitrarily spit planes and then had to rectify the ground loops. 70Hz is relatively low speed. If each device on the digital side has it's own capacitor to debounce it, you are unlikely to see feed through on the supplies lines.

For 1GHz sampling ADCs, we generally have matched line lengths and no planes due to how much charge "sloshes" around on the planes.

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  • \$\begingroup\$ I like how you use the term "sloshes" weirdly enough that gave me a pretty good analogy and mental image of what is happening. So you are saying that its better to keep my current setup rather than me having the chance of not doing it properly? \$\endgroup\$ – Jake quin Apr 12 at 9:02
  • \$\begingroup\$ @Jakequin I would just keep what you have as I do not believe that you you'll have an issue for the speeds at hand. You can basically spend an infinite amount of time for a marginal serials of improvements. When I made mixed-mode ICs, the whole key to success was charge balancing. BTW, the Murata NFE61PT102E1H9L is a really good EMC filter that I use heavily when I must tie planes together. You also can use them on the supply lines. For ADCs, you will see noise as a function of the IO clock and sample clock. You just filter out those frequencies for single-gnd plane design. \$\endgroup\$ – b degnan Apr 13 at 18:03

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