I'm learning a CPU architecture and currently found some high-level description of Intel x86_64 CPUs architecture. By the high level description I mean something like the following micro-op flow (might be wrong, this is how I currently see it):
1. Fetching code from memory 2. Caching the code in L1I cache 3. Activating Legacy Decode Pipeline 4. Put the decoded micro ops into the Decoded ICache and to the micro-ops queue (a.k.a IDQ) 5. Send micro-ops from the micro-op queue to RAT (a.k.a Renamer) 6. Allocate necessary resources and send micro-ops to the Reservation Station (a.k.a. Scheduler) 7. Dispatch micro-ops to the appropriate port 8. Write the result of the micro-ops to the writeback bus 9. Retire the micro-op
The question is if it is possible for micro-op to pass multiple pipeline stages for a single clock cycle?
A bunch of micro-ops are fetched from the Decoded ICache and put to the IDQ then the Renamer moves the micro-ops to the RS during the same clock cycle
Renamer moving a micro-op from IDQ to RS and then RS dispatches the micro-op to an issue port during the same clock cycle
When OOO core finishes execution of a micro-op its result is written to the writeback bus and then the micro-op is retired during the same clock-cycle.
Is it technically possible?