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I am learning about VLSI static timing analysis (STA) and some applications of SDC commands. I'm probably still missing some big picture concepts, but my question is about "why" when it comes to using set_clock_latency.

I see from the command there is an option to specify the latency from -source (the originating point of the clock such as a PLL) to the point where the clock is defined (like a port pin), and then there is a different set of options to specify network latency (from the point where the clock is defined to the final clock pin of a flop).

What's a good use for this? When do you care about the latency between the source and port pin? Wouldn't caring about timing relative to the pin be good enough? I can see the -min/-max/-early/-late being useful, but couldn't these values get rolled up into a "set_clock_uncertainty" command?

And for network latency, isn't this something the tools should worry about since it's handling the clock tree synthesis? What is gained by me directing the tools, and what value would I even put?

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Your assumption on network latency is correct. If a tool is handling clock tree synthesis (CTS), we don't need to specify "ideal" network latency.

When do we need then?

Note that CTS is performed by a P&R (place and route) tool such as Synopsys IC Compiler. There is no clock tree in synthesis or post-synthesis STA (static timing analysis), the tools can't know actual clock latencies.

We specify ideal latencies, therefore synthesis/STA tools have more accurate input and give more accurate output. These ideal values usually come from past experience or previous P&R results.

Using the set_clock_uncertainty command for that purpose wouldn't be a good idea. Ideal network latencies are not needed in P&R (after CTS stage) or post-P&R STA, but clock uncertainty is.

If you define your clocks propagated in post-P&R STA, ideal network latencies are overridden1 and actual values are used. This brings more flexibility.

set_propagated_clock [all_clocks]

I have never needed to specify source latency, so my answer is about network latency only.

1: Valid for Synopsys tools, the behaviour can be different for other EDA vendors.

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