# FET based "zener amplifiers" It is described as a negative power supply, where R1, R2, Q1 and Q2 form a current sink and Q3 "amplifies" the zener voltage, keeping a stable voltage between its drain (GND) and source (out).

So I have a few questions. I'll start just with the current sink. I've reduced it and isolated it as below: 1) Can I call the current sink configuration a series feedback pair?

I know it has the benefits of the high output impedance of the JFET, and the high gain of the BJT which allows a proper negative feedback. So the way I see it works like this. In initial conditions, Q2 gate is assumed at 0V, since there is still no current flowing through Q1. So Q2 will allow a $$\I_{DSS}\$$.

At the next moment, R2 will have a $$\V_{BE}\$$ across it from Q1 as long as $$\I_{Q2}*R2>0.7V\$$. That should be enough to keep Q1 saturated and R1 will set Q1 collector current. The voltage drop at R1 will set the voltage at Q2 gate.

2) Should Q1 be really saturated? I can't see other way, since there is really no restriction for its base current.

It is also clear how negative feedback works. If $$\I_D\$$ in Q2 tends to increase, $$\V_{BE}\$$ in Q1 tends to increase, also increasing Q1 collector current, that makes $$\V_{GS}\$$ more negative and regulates the disturbance.

R3 is the load and operating current in the example is $$\\frac{V_{BE}}{R2}\$$ , calculated for a 2.5mA renders $$\R = 269\Omega\$$.

J2 at left of the circuit is there just to check the actual $$\I_{DSS}\$$ for this part in LTspice, and that is equal to 5.19mA.

Simulations showed excellent results, ranging from R3 short circuited (green) up to 4.48k (pink). Last step was to 5.6k (not displayed below), that started to reach the compliance voltage. 3) How is it possible that $$\V_{GS,Q2}\$$ goes down to -14.5V and there is still current flowing through its drain and source? According to this part datasheet: LSK489A, its pinch off voltage should be about -1.7V for a $$\V_{DS}\$$ of 10V at 25C. In my example, $$\V_{DS}\$$ ranges from -470mV for the 5.6k load to -14.3V for the short circuit. But any $$\V_{GS}\$$ more negative than ~ -1.7V should not allow the calculated current of 2.5mA in R2.

How is this possible and suggestions for fixing it, if needed. Changing R1? That still seems weird to me, because $$\V_{GS}\$$ and $$\I_{DS}\$$ are related by the

JFET basic equation: $$\ I_{DSS}(1-\frac{V_{GS}}{V_p})^2 \$$

Where $$\V_p\$$ is the pinch-off voltage.

So how is $$\V_{DS}\$$ of Q2 supposed to accomodate variations in voltage in order to keep the $$\I_{DS}\$$ when its $$\V_{GS}\$$ is being held by the voltage drop in R1?

I will elaborate further questions on the actual "zener amplified regulator".

EDIT1: fixed equations.

• I'm sure that the schematic is showing an N-channel MOSFET (enhancement type) not a JFET. And here you can find the analysis of a BJT's version electronics.stackexchange.com/questions/481308/…
– G36
Apr 11 '20 at 6:53
• Some considerations... Q3 does not amplify the Zener voltage; it acts as an "active diode" that follows this voltage by the help of a voltage-type negative feedback implemented by the Q2 voltage follower connecting the Q1 collector to its base. The high output impefance of Q2 is not because of the FET; it is due to the series negative feedback (R2 source degeneration). Q1 is not saturated; it works in active mode because of the voltage-type negative feedback. Visit also electronics.stackexchange.com/questions/483339/…. Apr 11 '20 at 10:25
• @G36, I understand, it caught my eyes as well. Doug Ford used this same symbol for JFETs all over this video. Since there is no standard for that, can't really call it wrong, despite JFET not having isolated gates as in his drawing. I get that a MOSFET should be used in Q3, but a JFET seems perfectly reasonable for the current sink, specially if one needs very low noise figures.
– tfm
Apr 11 '20 at 15:00
• For the JFET Doug Ford use a slightly different symbol.
– G36
Apr 11 '20 at 16:40

In order to drive a N-channel JFET into its saturation region, the following requirements must be met:

$$V_{GS} \le V_{GS(off)}$$

$$V_{DS} > V_{GS} - V_{GS(off)}$$

$$V_{GS} \le -1.17V \rightarrow fulfilled$$

$$-7.35 > -7.4V + 1.17V=-6.23V \rightarrow unfufilled$$

NOTE: $$\V_{GS(off)}=-1.17V\$$ comes from the model implementation. Right click on it and you can see its properties. All the other values comes from your first simulation.

EDIT #1

Although not the most elegant solution, if you still want to use a NJFET, you have to ensure that the drain voltage of the FET is not fixed by the $$\V_{FWD}\$$ of the BJT. I just added some random values, and you would have to optimize it: EDIT #2

Here is a circuit similar to the one, shown in the video. (After watching the end of the video, I am almost sure that he is using a MOSFET instead of a JFET)

How it works

As you already explained, the components $$\R_G\$$, $$\M_1\$$, $$\Q1\$$ and $$\R_b\$$ form a controlled current sink. Disregarding the upper section for the moment, once the circuit is turned on, the source voltage of the MOSFET $$\M_1\$$ increases until it reaches $$\\approx 650mV\$$, thus turning on the BJT $$\Q_1\$$, which provides a negative feedback, which in turn reduces the $$\V_{GS}\$$ of the $$\M_1\$$.

There are two requiremts which must be fulfilled for the current source.

$$R_b > \frac{650mV}{I_{sink}}$$

AND

$$R_b > \frac{R_t\cdot 650mV}{V_{cc}-V_Z-650mV}$$

First condition ensures that there's enough current through $$\R_b\$$ to turn on $$\Q_1\$$, whereas the second one ensures that the voltage across $$\R_b\$$ is large enough to turn on $$\Q_1\$$.

The upper section of the circuit works as follows:

During start up the zener $$\D_1\$$ ensures that the gate voltage of $$\M_2\$$ is $$\\approx - V_Z = -4.7V\$$. At this moment the mosfet is on, and its source voltage starts to ramp ump until its $$\V_{GS} < V_{th}\$$ which yields an output voltage $$\V_{out}\approx -4.7V - V_{th} = -7V \$$ • @Hearth thanks for pointing that out :-) Apr 11 '20 at 11:19
• @vtolentino $V_{GS_{(OFF)}}$ equals vto in LTspice model, right? That would be -1.13V for this part, and datasheet shows a $V_{GS_{(OFF)max}}$ of -3.5V. So the reason there is current running through Q2, despite $V_{GS}$ at about -14V (well below the cut off voltage), is that the drain voltage is held approximately at the same voltage as the gate. For ex., using a 2.24k load, $V_{GS} = -8.84V$ and $V_{DS} = -8.74V$, so there is no reduction in substrate current. So based on that, I assume Q2 is not working as it should, in saturation region. How can I fix this still using a JFET?
– tfm
Apr 11 '20 at 16:48
• You cannot fix it because for a JFET the voltage at the gate needs to be lower than the voltage at the source. Thi is why you shoude use a MOSFET insted.
– G36
Apr 11 '20 at 17:21
• @HW_SW_Engineer exactly, $V_{to} = V_{GS_{OFF}}$. As for your second statement, it is wrong, because you are not considering the pinch off voltage, meaning $-8.74V < -8.74V + 1.17V = -7.67V$. I will updated my answer Apr 11 '20 at 17:23
• Understood it. Can I call this current sink configuration a series feedback pair?
– tfm
Apr 11 '20 at 17:51