# Slope compensation in current mode control

There is something a little bit confusing to me between papers dealing with the theory of external slope compensation in current mode control of SMPS and application notes dealing with implementation (Practical side) of current mode SMPS.

*In the theory, when we talk about external ramp compensation, we draw it on the graphs as a ramp with a negative slope (it is like if we subtract some amount of current from the inductor current). I understand that we have to inject an external ramp with a negative slope.

*In practice, as I have seen it in many applications, like MCP1630 from microchicp, or "designing ramp compensation NCP1200 from ONSEMI", the ramp is designed from a driver signal (square wave) using a simple way by an RC circuit and a diode like the one shown bellow. The ramp generated by this circuit with a positive slope is directly injected to the sense current pin of the IC using two resistors to add the inductor current and the ramp signal.

So my question is: What did I miss from the two descriptions. Why do we talk in theory about injecting ramp Se with a negative slope to get rid of sub-harmonics, and in practice we add a ramp Se with a positive slope?

• a negative ramp added into one input of a comparator is the same as a positive ramp into the other input. Can you verify whether you're talking about the same sense input? Apr 11 '20 at 10:42
• The ICs have one input pin for current sensing and and external ramp addition, for example if you look to the data sheet of MCP1630, will confirm that Apr 11 '20 at 10:49

Both approaches are mathematically similar. The below drawing shows how subtracting a voltage ramp from the feedback pin (or adding a negative ramp to the feedback pin) is similar to adding the same ramp to the current-sense information:

In the first case, you reduce the duty ratio by dynamically reducing the setpoint within the switching period. As such, the current sense voltage will meet the toggling point sooner since the setpoint is falling. The comparator trips, imposing a smaller duty ratio than without an external ramp.

In the right-side illustration, the setpoint is fixed but you "accelerate" the ramping voltage by adding another external ramp to it. Similarly as in the above, the resulting waveform will touch the fixed setpoint sooner, effectively reducing the duty ratio.

In both cases, you "fool" the comparator by making it believe there is more voltage developed across the sense resistance $$\R_i\$$. As you add an artificial ramp $$\S_e\$$, the modulator gain which is $$\G_{PWM}=\frac{1}{(S_e+S_n)T_{sw}}\$$ reduces in the current loop path and forces crossover at a lower point where phase margin is improved. As a result, the sub-harmonic poles present in the control-to-output transfer function are damped, reducing the peaking at half the switching frequency.

The $$\RCD\$$ method you have shown and used in the NCP1200 is a way to produce a quasi-linear ramp from a low-resistance source, the drive output. As such, the ramp can also be of low impedance and the noise immunity of the whole supply improves. This technique - proposed by Ray Ridley in 1990 - was offering a better performance than the solution promoted by Unitrode at that time which consisted of buffering the oscillator ramp and injecting the signal in the CS pin. However, an oscillator deals with low currents and trying to play with this sensitive circuit by adding an emitter follower was often causing problems hence this alternate solution. Modern ICs now either include internal slope compensation or lets you adjust it via a resistance in series with the CS pin (see NCP1250 for instance).

I thought it would be useful to add another sketch with a duty ratio calculation in both cases. In the first one, the ramp subtracts from the setpoint $$\V_c\$$ imposed by the control loop. In the second case, the ramp is added to the current-sense information and the converter believes there is enough voltage across the sense resistance. Please note that the maximum peak current capability if affected by the amount of injected ramp. It is very likely that the power supply output current capability is reduced once slope compensation is added so something to keep in mind during laboratory experiments: