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I'm attempting to minimize the \$S_{11}\$ of a \$10\,\text{pF}\$ DC blocking capacitor on a microstrip trace for my signal frequency range, which is \$5.3-5.9\,\text{GHz}\$. My microstrip trace width is \$0.38\,\text{mm}\$.

I started by using a 0402 cap (\$0.5\,\text{mm}\$ width), but the performance was poor (results below). I'm using OpenEMS to simulate the behavior. Using a 0201 cap (\$0.3\,\text{mm}\$ width) improved the performance significantly, but still yielded worse performance than I would like.

To improve the performance further, I used a ground cutout below the capacitor. Since I didn't know the size to use, I let Scipy choose a cutout width that minimized \$S_{11}\$ in my frequency range. I chose the length of the cutout to be the full extent of the capacitor+pads in all simulations. Interestingly, the optimizer came back with a really large cutout: almost \$4.5\,\text{mm}\$. Sure enough, though, this improved the performance dramatically in the signal frequency range at the expense of broadband performance. Here's a bird's eye view diagram showing the cutout, followed by a plot of the results.

enter image description here

enter image description here

The Qucs line is a Qucs simulation that I've used as an ideal baseline to compare against the other simulations.

Does this result seem reasonable? Previously, I'd thought cutouts were only used when the capacitor was wider than the signal trace, and in that case, the cutout would be much smaller than it is here.


EDIT

I'm using Oshpark's 4-layer process, which has a dielectric of 3.64 (substrate is FR408), substrate height of \$0.1702\,\text{mm}\$ (I'm using the 1st and 2nd copper layer) and 1oz copper top layer and 0.5oz copper 2nd layer.

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  • \$\begingroup\$ Can you share a diagram of your microstrip geometry (dielectric height, Dk, etc)? \$\endgroup\$ – The Photon Apr 11 '20 at 19:08
  • \$\begingroup\$ I've added the dimensions in an edit to the original post. Would a diagram be helpful as well? \$\endgroup\$ – MattHusz Apr 11 '20 at 19:12
  • \$\begingroup\$ You've created an LC resonant filter. If you want to use this, consider that the capacitor value, dielectric height, dielectric constant, and copper width will vary due to manufacturing tolerances, and do some tolerance analysis before you choose a design. \$\endgroup\$ – The Photon Apr 11 '20 at 19:15
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    \$\begingroup\$ @MattHusz, it would depend on the system requirements. Also, we're doing digital work so usually we need a broadband match rather than just a notch at one operating frequency. \$\endgroup\$ – The Photon Apr 11 '20 at 19:44
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    \$\begingroup\$ @Ale..chenski, Are you sure that the parasitics in the Murata model don't include effects from some particular mounting geometry? \$\endgroup\$ – The Photon Apr 12 '20 at 2:07
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Does this result seem reasonable?

It is reasonable as a simulation result.

By cutting out the ground plane, you force the return currents to flow further from the signal currents. This increases the inductance of the structure. With sufficient inductance and the lumped capacitor you form an LC circuit that at some frequency looks like a short between one section of transmission line and the the other. Using your optimization procedure you adjusted the geometry to make this frequency equal to your operating frequency.

Practically, it might not be a good idea to try to use this effect to match your line because

  • The resonant frequency will be affected by manufacturing variation of the dielectric thickness, dielectric constant, copper thickness, capacitor value, etc.

  • There is some uncertainty about the capacitor model. You haven't said what model you use (lumped capacitance, RLC equivalent circuit, 2-port s-parameters, ...) but very likely the model provided by the manufacturer includes some effect from the test fixture they mounted it in during characterization. How to back-out those fixture effects to predict the behavior in your circuit geometry is a tricky question.

As mentioned by Ale..chenski in comments, we more often use ground plane cut-outs for pad matching when the pad width is greater than the transmission line width we're trying to match.

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  • \$\begingroup\$ Are there any compensation techniques for when the capacitor width is less than the microstrip width? I'm debating whether to use a 0201 or 0402 cap for my test prototypes. I'm tempted to go with the 0201 which will have lower inductance and gives a better baseline simulation result (simulation uses a lumped capacitance model and ignores parasitics like ESL and ESR). \$\endgroup\$ – MattHusz Apr 13 '20 at 19:36
  • \$\begingroup\$ I can, of course, prototype both but I'd like to keep costs down, especially if I need to try several different cutouts for the 0402. \$\endgroup\$ – MattHusz Apr 13 '20 at 19:43
  • \$\begingroup\$ To attempt to answer my own question, I expect the way to compensate for a small cap would be to bring the coplanar ground plane closer. However, like the rest of this I expect this would be difficult to achieve repeatable results given the manufacturer tolerances. \$\endgroup\$ – MattHusz Apr 16 '20 at 5:41

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