I'm attempting to minimize the \$S_{11}\$ of a \$10\,\text{pF}\$ DC blocking capacitor on a microstrip trace for my signal frequency range, which is \$5.3-5.9\,\text{GHz}\$. My microstrip trace width is \$0.38\,\text{mm}\$.
I started by using a 0402 cap (\$0.5\,\text{mm}\$ width), but the performance was poor (results below). I'm using OpenEMS to simulate the behavior. Using a 0201 cap (\$0.3\,\text{mm}\$ width) improved the performance significantly, but still yielded worse performance than I would like.
To improve the performance further, I used a ground cutout below the capacitor. Since I didn't know the size to use, I let Scipy choose a cutout width that minimized \$S_{11}\$ in my frequency range. I chose the length of the cutout to be the full extent of the capacitor+pads in all simulations. Interestingly, the optimizer came back with a really large cutout: almost \$4.5\,\text{mm}\$. Sure enough, though, this improved the performance dramatically in the signal frequency range at the expense of broadband performance. Here's a bird's eye view diagram showing the cutout, followed by a plot of the results.
The Qucs line is a Qucs simulation that I've used as an ideal baseline to compare against the other simulations.
Does this result seem reasonable? Previously, I'd thought cutouts were only used when the capacitor was wider than the signal trace, and in that case, the cutout would be much smaller than it is here.
EDIT
I'm using Oshpark's 4-layer process, which has a dielectric of 3.64 (substrate is FR408), substrate height of \$0.1702\,\text{mm}\$ (I'm using the 1st and 2nd copper layer) and 1oz copper top layer and 0.5oz copper 2nd layer.