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I found this document online, which shows an interesting USB routing topology that I have not seen before. The 4x superspeed lines go straight from the USB3 connector to the SuperSpeed IC, but the USB2.0 lines go off to a USB2.0 hub, where one of the down stream ports connects back up to the SuperSpeed IC. I can't find any other examples of this online... is this allowed? I would have probably just designed in a USB3.1 SuperSpeed hub, and not split the signal lines off.

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  • \$\begingroup\$ Clearly it works. Seems quite useful. \$\endgroup\$ Apr 11, 2020 at 20:49

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This design uses one USB 2.0 channel for the high-speed data channel of USB 3.0 and another for FT2232 for jtag/uart/spi for programming and debugging.

Traditionally FT2232 is usually connected a independent USB 2.0 port, but this design multiplexes it into the main USB port using a USB 2.0 Hub IC.

Super-speed channel is not split because FT2232 is a full-speed chip and can not make use of the super speed channel.

But in the proposed FPGA host interface scheme, instead of connecting the USB 2.0 signals (D+/D-) directly to the upstream connector, a USB hub (USB2422 – A 2- Port USB 2.0 Hi-Speed Hub Controller from Microchip Technologies) is inserted in between. This allows the USB2.0 bus available on USB C connector to be shared between FT601 and the FT2232H USB 2.0 FIFO bridge acting as the sideband processor (See figure 3 below). In this scheme, the SPI signals available on FT2232H Bus A are connected to the SPI bus used for FPGA configuration. A General Purpose IO on this bus is also connected to PROG_B of the FPGA to allow the host to reset the FPGA. Optionally, additionally available General Purpose IOs on FT2232H can be used to monitor the FPGA configuration progress by observing the DONE signal.

This solution works because the high/full/low-speed channel and super-speed channel work independently and not simultaneously on one endpoint, so the FT601 chip either sees itself directly connected to the super-speed channel, or to the high/full/low-speed channel via a hub. One more hoop in the high/full/low-speed channel than the super-speed channel is not an issue.

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USB3 endpoints (upstream-facing ports) are allowed to have only standard (LS/FS/HS), only SuperSpeed, and of course, both.

USB3 downstream-facing ports must support standard and SuperSpeed, or standard only, but not SuperSpeed only. This is to allow backwards compatibility with legacy LS/FS/HS devices.

Further, you can’t ‘split’ a USB3 downstream facing port into two endpoints, one SuperSpeed and one standard. It is only allowed to negotiate a connection to one device. To split it, a hub is required.

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  • \$\begingroup\$ Can you clarify your last point? It sounds like you are saying this shouldn't work. \$\endgroup\$
    – alex
    Apr 13, 2020 at 16:23
  • \$\begingroup\$ It’s not an allowed topology under USB3 rules. It will not do the negotiating with USB3 correctly. It would work only with USB2. \$\endgroup\$ Apr 13, 2020 at 18:20

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