If a via is meant to carry current why not go for a solid copper filled via than a plated via (which is hollow/nonconductive at the center)?

After all in electrical engineering, we dont go for a hollow conductor saying it will be cheaper. We just change the conductor size ( or use more no: of conductors) as per the current.

Why cant we follow the same approach to via?


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    \$\begingroup\$ your proposal sounds harder to manufacture. \$\endgroup\$ Apr 13, 2020 at 8:00
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    \$\begingroup\$ Copper is not 'poured' it is deposited, sort of like snowflakes. Just as with snowflakes is difficult to fill a narrow deep hole consistently. \$\endgroup\$
    – Oldfart
    Apr 13, 2020 at 8:16
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    \$\begingroup\$ liquid copper is too hot and shrinks too much when it cools. \$\endgroup\$ Apr 13, 2020 at 8:18
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    \$\begingroup\$ Micro-vias (that only go from the surface layer to the next in multi-layer PCBs) are often sold copper filled; that is a bit easier to do as the via depth is only about 100 microns to 150 microns in situations that require them. The shape is also important - they are often a modified conical shape. \$\endgroup\$ Apr 13, 2020 at 9:32
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    \$\begingroup\$ Lets not stop at solid copper, can we just use silver with gold plaiting for the layers, and via fill right away to maximize both thermal and electrical conductivity? It all comes down to time and distance... Which really means money and time. \$\endgroup\$
    – MadHatter
    Apr 13, 2020 at 13:23

7 Answers 7


High-current vias are relatively infrequently needed.

If they are needed, and the current is higher than a regular via would handle, it is very easy to insert a through-hole pin and solder both sides. This guarantees good conductivity with no risk of inclusions in the via, and it can be done automatically by a pick-and-place machine and flow-soldering.


There is copper filled via in older technologies, I donot think you can do that now, if i remember correctly it is used for BGA . The problem is higher manufacturing cost and difficulty and the thermal expansion issues that could cause cracks in solder joints

From PCB universe:

This is an older callout sometimes seen on legacy products. The original idea was to call for this as a way to have a copper conductive filled via. The problem with this process is that the holes must be extremely small to make this feasible since the copper used to plate a via closed will also plate on all copper features on the board"

That means the board will become 3-4oz which makes small features and clearances impossible.

Another drawback is the extreme difficulty in plating the entire barrel of the hole evenly. A hole barrel will tend to plate faster toward the top and bottom of the hole which means a hole may look sealed but in the center there is trapped air and/or fluids which will outgas when exposed to assembly temperatures."

See image below:

enter image description here


If a via is meant to carry current why not go for a solid copper filled via than a plated via (which is hollow/nonconductive at the center)?

Because a plated via hole is "good enough". There are a number of processes needed to fabricate a bare PCB and each one takes money and time.

  1. Print onto laminate the areas to etch
  2. Etch
  3. remove "black ink" used to protect traces
  4. Repeat for as many core as there is
  5. Repeat for as many foil layers as there is
  6. Bond
  7. Drill PTH
  8. Plate (NOTE via size is finished so the fab will drill to larger and align to the plating thickness)
  9. Drill NPTH

Its a bit more than that, but generally that is the process. So while you are correct if via's are meant to carry current why not fill them with copper, its a bit more than that. Via's carry current but if the current you are carrying is uA (due to signals) or ~5A, then why are more process steps needed? If you need 10A put 2 0.3mm via's down. What more current? increase the diameter to trade off surface area and via size.

During the playing process could they fill the via completely? no and that why it isn't done. If they were to keep a PWB in the bath for longer, the thickness would build up and equally the via's would start to fill. At some point it would be completely filled wouldn't it? yes, but with what

  1. 100% copper
  2. fluid ?

And therein lies the problem. There is no way to guarantee the via's would be solid. If it started to tent before it was completed, when the PWB was populated there is a possibility that the contained fluid would pop. Even if there was no fluid there is no way to guarantee a full via so it isn't done.

However, you can fill the via's with epoxy and there are two types used

Electrically Conductive

DuPont CB100 Tatsuto AE3030. These are silver coated copper particle’ filled epoxy matrix and thus help improve the electrical conductivity.

Electrically Non-Conductive

Peters PP2795 epoxy and San-Ei Kagaku PHP-900 epoxy. These are electrically non-conductive but are good thermally and are typically used to improve the thermal characteristic of thermal via's.

The downside? Cost and additional considerations with regards to CTE


You can, but it adds more steps to a manufacturing process. So the question becomes, how important is it to you, and what are the alternatives. In terms of importance: For electrical conduction, there isn't much difference over <2mm, and it's just easier and less expensive to add a second via. For heat conduction, you need a larger volume of metal, so we often use metal core boards instead. In terms of alternatives, you can melt low temp solder paste into those holes.... That's not as conductive as copper, but it's probably good enough.


First of all I think most people have trouble getting a feel for how much current a typical via can actually conduct since its harder to imagine than let's say a wire.

A typical via with a drillsize of around 0.3-0.4 mm is able to conduct 2A easily. Increasing the drill size increases the current capability although not linear... 0.6 mm does something like 3A out of the top of my head. Tell me, what kind of signals you are using which exceed that limit.. If you have let's say a high current application then it is common to use a array of vias and thus expanding the current capabilities of a plane or something.. And since power density of a package goes hand in hand with the size of the package this isnt usually an issue. Fun side note here, as current increases further and further it is actually more important how the current spreads over an array of via's.. Adding more vias after a certain point does not yield more current capability since paralleling more vias will not result in a power impedance path.. This often results in really surprising results when you are performing simulations and I have seen results in which half of vias in an array did barely anything.. So you often tweak an via array for high current paths..

As already stated above, producing a copper filled via is more complicated and thus expensive. And since there is often no reason to do so from current perspective it is just not done very often. If they do use some kind of filled vias its way more likely this is because of assembly issues to prevent solder from leaking in the vias or to improve thermal performance.


Note that at RF frequencies, there is a skin-effect issue that comes into play where the high frequencies have trouble traveling through the plane and preferentially travel around the edges instead (which can be very far away if it is a plane). Having the via be hollow helps alleviate this in a plane since it can travel along the inside of the via.

This won't really be an issue for most high current applications which work at much lower frequencies though.

High Frequency Characteristics of Solder-Filled Vias

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    \$\begingroup\$ This is simply not true. Having metal at the core of the conductor core does not hurt, and conversely removing metal does not help. \$\endgroup\$ Apr 13, 2020 at 18:28
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    \$\begingroup\$ @JeffreyNichols If for some reason the current enters the plane from the wrong side it could. Granted, this is almost never an issue since most traces have a nearby edge to travel around which also accommodates allows the current to reach the right side if it it connects to a plane without an edge. But, if for some reason, you had a solid via connecting two planes, high frequency current entering the far side would have to travel around the edges, and outside of the via to get to the far side of the other plane. With a hollow via it just travels along the inside. \$\endgroup\$
    – DKNguyen
    Apr 13, 2020 at 18:35
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    \$\begingroup\$ @JeffreyNichols electronics.stackexchange.com/questions/432073/… \$\endgroup\$
    – DKNguyen
    Apr 13, 2020 at 18:40
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    \$\begingroup\$ Skin effect means that "interior" conductor contributes less to admittance than it would have otherwise (maybe far, far less if it's several skin-depths from the surface). It does not mean that it will ever have a negative impact. \$\endgroup\$
    – hobbs
    Apr 13, 2020 at 20:15
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    \$\begingroup\$ @DKNguyen - you really should quantify your answer. It's not true that "higher frequencies cannot travel through a PCB plane or trace". Take an 0.5 oz copper trace as an example. Thickness of this trace is ~17.5 um. At 100 MHz the skin depth of copper is 6.52 um, and so the current/signal travels through much of the cross section of the trace. At 1 GHz, the skin depth is 2.06 um, and so it's fair to say that most of the current flows along the surface. Finally, OP was asking about high currents, which I suspect are way below even to 100 MHz frequency I used. \$\endgroup\$
    – SteveSh
    Apr 15, 2020 at 16:10

Vias are created using a plating process. Creating thicker plating takes more time to manufacture. Filling the vias solid takes more time than the standard plating process. It can be done, but usually one needs to have good reason to justify the added expense.

There are companies like NetVia group LLC that can plate the vias (evenly with no voids) until they are filled solid with copper.

This is typically done as an alternative to epoxy filling. Either for more current, thermal conductivity, or for putting vias in pads without stealing solder paste.

Though plating solid takes more time, it can be a good alternative to epoxy filling. Board houses may not want to stock rarely used, expensive, epoxies with short shelf life. Also waiting for epoxy to cure may take more time than just plating solid.


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