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I want to build an electronic analogue SPDT switch that switches on a trigger/rising edge. A SPDT CMOS switch control is held high or low for either output.

This could be done with 2 outputs of a CD4017 + inverters to switch the switch states but there must be a more elegant solution than that.

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  • \$\begingroup\$ Use an analogue switch aka transmission gate. \$\endgroup\$
    – Andy aka
    Apr 13, 2020 at 10:56
  • \$\begingroup\$ @Jay does it toggle on rising edge or go to a particular state? What is the maximum rate of rising edges, max clock rate? \$\endgroup\$
    – scorpdaddy
    Apr 13, 2020 at 12:25
  • \$\begingroup\$ @Jay could you not use a DFF, with /Q going to D input and your clk to clk? Like SN74AUP1G80? \$\endgroup\$
    – scorpdaddy
    Apr 13, 2020 at 12:32
  • \$\begingroup\$ @scorpdaddy it should toggle. max clock rate... 10Hz? maybe a little higher, nothing high speed. Flip flop seems like its the answer but the logic kinda confuses me. clk rising edge > /Q goes high > D goes high > /Q goes low ... how would the next rising edge end up holding /Q high? \$\endgroup\$
    – Jay
    Apr 13, 2020 at 21:24
  • \$\begingroup\$ @scorpdaddy Did you mean to post a flip flop chip with Q and /Q outputs? A Toggle flip flop looks like it will do the trick. \$\endgroup\$
    – Jay
    Apr 13, 2020 at 21:46

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