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enter image description here Is it ok to put the vias like that, help with something for a high current? The thickness of the route is 400 mil (200 on top and 200 on bottom). It is necessary to support ~15A. In the right corner the pad is smaller then the route, is that ok, i can put the vias in both sides? What helps if i put vias on the power routes and GND routes?

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  • \$\begingroup\$ I would definitely try to keep those high-voltage traces as far away from each other as possible. You could try to make that round part (the one you circled) more like flat so that it at least a little bit further away from the other contact . Also, when such high voltage traces are that close, the industrial practice is to drill a line between them so that no foreign materials (including moisture) collecting on the surface would eventually make a conductive path and burn the board. \$\endgroup\$ – Edin Fifić Apr 13 at 19:50
  • \$\begingroup\$ Thx!! The distance between those routes is about 100mil in the photo, or more \$\endgroup\$ – Elvis Apr 13 at 20:14
  • \$\begingroup\$ According to my calculations those 6 vias only increase the amount of through-hole conductance by 10% over the large hole, and that doesn't take into account the wire/connector (which surely is by far the biggest contributor). Seems pointless. \$\endgroup\$ – Bruce Abbott Apr 15 at 2:19
  • \$\begingroup\$ @Bruce Abbott I this case, what should I do? Is it necessary to put more vias? \$\endgroup\$ – Elvis Apr 15 at 15:47
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It is a good idea to do that, my recommendation would be for you to calculate the effective width of copper connecting layers in each via (perimeter of the hole * thickness of the plating) so that it matches a couple of times the width of the trace, make those holes as small as possible and put no more.

The reason for that is that if you put too many holes and those holes are big, then in the effective section of the trace in which you are placing them may be substantially reduced, there are other ways to avoid that like distributing the holes over a bigger area, yet you also want to keep them close to the connection point.

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  • \$\begingroup\$ Thx, they are as small as possible. Is it necessary to put vias on the GND route as well and what's happening with the current if the pads of components are also small or vary small ? \$\endgroup\$ – Elvis Apr 14 at 18:41
  • \$\begingroup\$ I would do the same whenever you have a trace with a lot of current running, if your return path is a trace instead of a ground plane, i'd say yes, do it, in the case pads are very small then you will have that localized area with high dissipation, however if then it widens and you have a large area of copper then the heat will spread through it and won't be a problem, you can see that happening when you use thermal relief, a small zone with very thin traces which under normal circumstances don't affect the performance of the layout, the exceptions being rf and very high amounts of current \$\endgroup\$ – diegogmx Apr 14 at 19:14
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definitely and it is standard practice. The key is to place enough, with suitable diameter, such that you do not take away too much copper (swiss cheese your design) such that the end result is a path with lower copper

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