preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.)
However, I am very new at Verilog and also have never used VHDL or any other HDL.
I want to design an 8 bit up counter which will count up when CLK pulse hits(rising edge).
My understanding on the design and simulation of such a circuit in Verilog is as follows,
First I should design a module which will be my box with inputs and outputs to do the desired job. Then I somehow have to simulate it using a testbench module(I am not sure about this).
So, I designed a module.
Here is my code:
module up_counter( count, clk, ); input clk; output [7:0] count; reg [7:0] count; always @(posedge clk) begin count = count + 1; end endmodule module up_counter_tb; reg clk; wire [7:0] count; // I really don't understand why making this a wire instead of a reg, but I saw as wire everywhere. up_counter uut( .clk (clk), .count (count) ); initial begin clk = 0; end always begin #10 clk = ~clk; end endmodule
The code above compiles fine, and I run the simulation in Modelsim by,
Simulation comes, I pass
count to waveform displayer, I run the simulation,
clk seems fine, it roams between 1 and 0 nicely. However, I cannot observe any change in
count. Its value is alway
To me, my code seems correct. I assume, I am using a data type or a flow mechanic very specific to Verilog(or a HDL) in a wrong way.
Any help on pointing the mistake here would be appreciated.