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preamble: I think I have enough understanding of logic circuits and enough experience in programming from other languages(C, python, etc.)

However, I am very new at Verilog and also have never used VHDL or any other HDL.


I want to design an 8 bit up counter which will count up when CLK pulse hits(rising edge).

My understanding on the design and simulation of such a circuit in Verilog is as follows,

First I should design a module which will be my box with inputs and outputs to do the desired job. Then I somehow have to simulate it using a testbench module(I am not sure about this).

So, I designed a module.

Here is my code:

module up_counter(

count,
clk,

);


input clk;
output [7:0] count;
reg [7:0] count;

always @(posedge clk) begin

  count = count + 1;

end



endmodule


module up_counter_tb;

  reg clk;

  wire [7:0] count; 
// I really don't understand why making this a wire instead of a reg, but I saw as wire everywhere.


  up_counter uut(

  .clk (clk),
  .count (count)

  );

  initial begin
    clk = 0;
  end

  always begin
    #10 clk = ~clk;
  end


endmodule

The code above compiles fine, and I run the simulation in Modelsim by,

vsim up_counter_tb

Simulation comes, I pass clk and count to waveform displayer, I run the simulation, clk seems fine, it roams between 1 and 0 nicely. However, I cannot observe any change in count. Its value is alway xxxxxxxx.

To me, my code seems correct. I assume, I am using a data type or a flow mechanic very specific to Verilog(or a HDL) in a wrong way.

Any help on pointing the mistake here would be appreciated.

Thanks.

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  • 1
    \$\begingroup\$ Hint: You made sure the initial value of clk was zero before you started toggling it. Did you do the same for count? \$\endgroup\$ – The Photon Apr 14 '20 at 14:11
  • \$\begingroup\$ @ThePhoton actually, I wanted to try that, however, adding a count = 8'b0; right below the clk = 0; statement yields an error of : ** Error: /home/muyustan/altera/13.1/modelsim_ase/bin/up_counter.v(40): (vlog-2110) Illegal reference to net "count". \$\endgroup\$ – muyustan Apr 14 '20 at 14:13
  • \$\begingroup\$ @toolic it was another thing everybody was using in their example, however, I really don't want to have a reset input on my design, it seems meaningless to me. I am sorry if it sounds silly. \$\endgroup\$ – muyustan Apr 14 '20 at 14:14
  • \$\begingroup\$ @toolic I just did the assignment in an initial block in main module instead of the inside of test bench module and it worked. Would it be a more preferable way over using your way in your latest comment? \$\endgroup\$ – muyustan Apr 14 '20 at 14:20
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    \$\begingroup\$ You should make sure count is initialized in the the up_counter module, not the testbench. If you don't want a reset input on your design, then you can use an initial block like you did for clk in the testbench. \$\endgroup\$ – The Photon Apr 14 '20 at 14:22
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From the comments on my question, the problem was about not initializing the count to a known state.

So, adding a count = 8'b0 in an initial block in the main module(up_counter) solves the problem.

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