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Given the fact that the clock frequency is about one GHz and the corresponding wavelength is about the same order of magnitude (velocity of propagation is lower than 3 * 10^8 m/s inside the chip) with chip dimensions, is care taken care of to suppress signal reflections inside the chip?

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  • \$\begingroup\$ Did you actually calculate the wavelength at 1 GHz and compare it to chip dimensions? Also, the velocity of propagation in a wire is not equal to the speed of light in a vacuum. \$\endgroup\$ Commented Apr 14, 2020 at 14:11
  • \$\begingroup\$ λ=10^8/10^9 = 10 cm. I am assuming velocity equals 10^8. Chip dimensions is one third or one fourth of the wavelength? Am I geting this right or wrong? \$\endgroup\$ Commented Apr 14, 2020 at 14:16
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    \$\begingroup\$ Some SoC devices have internal bond paths measured in inches (I first encountered one in 2000); for high speed inputs there is often a termination on the die itself. \$\endgroup\$ Commented Apr 14, 2020 at 14:23
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    \$\begingroup\$ No, before the wire is so long that reflections become relevant you will have trouble meeting timing. In which case you add buffers in which case the path get shorter. \$\endgroup\$
    – Oldfart
    Commented Apr 14, 2020 at 14:29
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    \$\begingroup\$ If the signal propagates at 0.7c then the wavelength is roughly 15cm. For the sake of discussion let's say that a quarter wavelength is 4cm. So, if you wanted to use Manhattan-style wiring and get a wire length of 4cm you need a die that is somewhat larger than 2cm on each side, maybe an inch on each side. Pretty big but not impossible. However, it would be very unlikely to have a single uninterrupted wire from one corner of the die to another operating at 1GHz. High speed signals are distributed with many buffers in the path. \$\endgroup\$ Commented Apr 14, 2020 at 14:34

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Most traces inside of dies are pretty short relative to the wavelength. An individual x86 processor core at 14nm is only 3x4 mm, while even the longer traces connecting things like L3 cache slices between cores in the Intel die photos look to be only about 4-5 mm long. Compared to the wavelength (>40mm), that is pretty short. My guess is they're not terminated, and they've picked that spacing and die orientation specifically to avoid it, but I could be wrong.

Conversely things like off die links (memory, PCIe, etc) are impedance matched because the distances are much longer. AMD for example shows how they use on-die termination resistors for their chip to chip links in this diagram:

https://en.wikichip.org/wiki/File:amd_if-ifop-serdes.png

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hard to get reflections, when skin effect causes current crowding and the higher frequency edges are attenuated.

Skin depth in copper is about 35 microns, at 4MHz.

At 400 MHz, the depth is sqrt(100) smaller, at 3.5 microns.

At 100 * 400MHz, or 40GHz or 25 picosecond edge rates which is about what the faster MCUs have internally, the skin depth is sqrt(100) smaller still, at 0.35 microns.

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Now we should consider the aspect ratios of modern metalizations, where plasma etching is used ----- very steep sidewalls.

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  • \$\begingroup\$ How does the skin depth compare to the conductor thickness on a 1GHz integrated circuit? \$\endgroup\$ Commented Apr 14, 2020 at 17:08
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    \$\begingroup\$ 350nm is huge. Remember that modern IC technologies these days have feature sizes well under 100nm. \$\endgroup\$ Commented Apr 14, 2020 at 22:29

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