I am researching HV driver amplifiers for controlling piezoactuators. My background is in physics, so I am a bit out of my comfort zone here. I came across the following schematic and have been struggling to understand it.

HV amplifier

So with a bird's eye view I see an inverting opamp whose output goes to common collector (Q5) which then feeds to a common emitter (Q6), which acts as a shunt for current mirror (Q3/Q4), which supplies the push-pull output stage (Q1/Q2). Lets say Vcc=250 such that R3 sets the current mirror current to 500uA.

Assuming abs(Vin) is 5V, we have 5ma over R8 to virtual ground at pin 2 of IC1. This means that the circuit must supply a matching and opposite 5ma through R9 to maintain the virtual ground. Continuing to work backwards, this means that push/pull pair has to source or sink 5ma (plus whatever the load requires!) to make opamp IC1 happy.

This is the point where I start to lose my confidence. Based on the way Q5 is hooked up to IC1, I think it makes sense to think only of the current being sunk by pin 6 of IC1 (since it is attached to the base of an PNP Q5 it won't ever source current). From here the collector current of Q5 is shared over R6 and R7 (can solve using KVL so the drop over R7 and R6+diode drop are equal). The source page states "You can adjust R7 to minimize output dc offset voltage and slew rate", but I don't really understand how it achieves this? The lower R7 is, the more current Q5 has to supply (and IC1 has to sink) to get the desired end output. Does this mean R7 is setting the input impedence of the following stage?

To understand Q6's role I start with the case where Vin=0. Opamp IC1 will do whatever it needs to so that the collector current is the 500uA specified by the current mirror. When this is the case, the node between R4 and R5 is at "ground potential" and thus the output is at "ground potential". If Vin goes positive, IC1 will cause Q6 to turn more off, forcing current through Q1. The current through Q1 reduces Vce of Q1, driving the input more positive. The opposite of all of this happens with Q2 when the input goes negative. However, I don't understand quantitatively how the current through Q1 or Q2 translates to Vout.

D1/D2 serve to stabilize IC1 by limiting the excursion of IC1 pin 6 from ground. I get why these diodes have a stabilizing effect, but I do not understand why it is necessary in this case.

Okay so that is about as much as I have understood about this circuit. Any insights from you professional EEs out there would be greatly appreciated, especially resources where I might be able to learn more about circuits specifically like this.

Edit to add: Thank you Andy Aka for bringing it to my attention that I forgot to include the Falstad circuit simulation that I set up. It did help me to understand more of the circuit but some things still eluded me, hence the post.

  • \$\begingroup\$ resources - the best resource is a simulator. If you need help choosing one just ask in the comment area. \$\endgroup\$ – Andy aka Apr 14 at 16:04
  • \$\begingroup\$ Q5 and Q5 are the CE amplifiers. Also, we can view Q5 as DC "level shifter" for the Q6 stage (brings the DC level voltage down for Q6). Also, notice that Ic5 = Vbe/R7. And because this circuit has a global negative feedback loop. The DC conditions are set by "negative-feedback magic". And this circuit is stable without a miller-compensation capacitor only due to very large R6 resistance. R6 together with Cbe and (Av5*Ccb) create a low pass filter. \$\endgroup\$ – G36 Apr 14 at 16:32
  • \$\begingroup\$ About Q1 and Q2 (Emitter followers) electronics.stackexchange.com/questions/309936/… \$\endgroup\$ – G36 Apr 14 at 16:47

Not too complicated. Quite neat in fact:

Firstly: Q5 is an inverting amplifier stage implemented in PNP;

Then Q6, is another inverting amplifier stage, but implemented in NPN; these two together, give a high gain from the signal already amplified in the LF411.

But MJE340 / 350s are 300-volt-capable transistors, so form a "final amplification" stage - able to cope with +/- 300V rails - for the overall amplifier which is formed, by this stage cascaded after the LF411. (But the LF411 can only cope with plus or minus 12v levels, hence it's supply rails).

Q4 + Q3, is a classic current mirror: the base-junction-threshold voltages match, so the current defined by Q4 and R3 as a collector resistor, means that Q3's base junction is just nicely biassed to deliver the same current in Q3 as Q4 has (= 2x Vcc / 1000000 A) - two microamps per volt on the high voltage rail pair (Vcc / -Vcc).

The second stage of transistor amplification, Q6, thus sees the high impedance collector circuit of Q3 as a constant-current souce and R4 / R5 deliver a high-voltage (but-defined-low-current) -swing, at the junction of R4 and R5;

-- that node then drives Q1 and Q2 which are linked as a pair of opposed emitter-followers -- so Q1 conducts for upward swings and Q2 for downward;

  • net result, an amplifier with up to 600v output swing, but at managed current (programmed by R3 mostly), so that you can control the heat.

High voltage stages like this can easily overheat unless you plan dissipation carefully - heatsinking likely to be needed. Some detailed attention required to the thermal design.

Quite an elegant design. The discrete stage is modelled on the design practices analogue chips often use inside.

PS: R9 / R8 are the overall negative feedback defining the gain: which is set at 20 by their ratio.

PPS: Remember when trying to comprehend a circuit like this that the overall design is fundamentally defined, by the negative feedback loop: the fact that the output is fed back to input through a divider guarantees, that the internal stages will align themselves controlled by that fact. So when trying to make sense of each individual stage, try not to think of it as "pushing or pulling a certain current" - rather recognise which are the amplifying and which the buffering stages, and see them as a cooperative set of functions delivering the desired result. (Here, there are two separate needs: (1) amplification, and (2) coping with the high-voltage swing. So the output stage is designed to cope with (2), and the transistor ampifier and current mirror - as a "final" stage to the operational amplifier, deliver (1).

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D1 and D2 keep the op amp from saturating. This limits the voltage on the base of Q5.

When Vin is high, the op amp output goes low by 1 diode drop, activating Q5. Q5 turns on enough to supply current to the base of Q6, which likely saturates, pulling its collector to -Vcc. Q4 and Q3 constitute a current mirror, which is effectively a pullup in this circuit.

When Q6 is off, the current mirror will supply current to the base of Q1, which acts as an emitter follower to pull up the output. When Q6 is on, it pulls current from the base of Q2, which is an emitter follower pulling the output down. The emitter followers simply increase the available current.

R9 appears to limit the output voltage to 20 times the input voltage.

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  • \$\begingroup\$ Ah the current mirror as a pull-up makes sense. That is a useful way to look at it. Thanks! \$\endgroup\$ – Conner Phillips Apr 14 at 19:03

Could you follow up on how it worked? Did you have any issue with heat dissipation? Which DC power supply did you use for the +-Vcc rails?


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