I am researching HV driver amplifiers for controlling piezoactuators. My background is in physics, so I am a bit out of my comfort zone here. I came across the following schematic and have been struggling to understand it.
So with a bird's eye view I see an inverting opamp whose output goes to common collector (Q5) which then feeds to a common emitter (Q6), which acts as a shunt for current mirror (Q3/Q4), which supplies the push-pull output stage (Q1/Q2). Lets say Vcc=250 such that R3 sets the current mirror current to 500uA.
Assuming abs(Vin) is 5V, we have 5ma over R8 to virtual ground at pin 2 of IC1. This means that the circuit must supply a matching and opposite 5ma through R9 to maintain the virtual ground. Continuing to work backwards, this means that push/pull pair has to source or sink 5ma (plus whatever the load requires!) to make opamp IC1 happy.
This is the point where I start to lose my confidence. Based on the way Q5 is hooked up to IC1, I think it makes sense to think only of the current being sunk by pin 6 of IC1 (since it is attached to the base of an PNP Q5 it won't ever source current). From here the collector current of Q5 is shared over R6 and R7 (can solve using KVL so the drop over R7 and R6+diode drop are equal). The source page states "You can adjust R7 to minimize output dc offset voltage and slew rate", but I don't really understand how it achieves this? The lower R7 is, the more current Q5 has to supply (and IC1 has to sink) to get the desired end output. Does this mean R7 is setting the input impedence of the following stage?
To understand Q6's role I start with the case where Vin=0. Opamp IC1 will do whatever it needs to so that the collector current is the 500uA specified by the current mirror. When this is the case, the node between R4 and R5 is at "ground potential" and thus the output is at "ground potential". If Vin goes positive, IC1 will cause Q6 to turn more off, forcing current through Q1. The current through Q1 reduces Vce of Q1, driving the input more positive. The opposite of all of this happens with Q2 when the input goes negative. However, I don't understand quantitatively how the current through Q1 or Q2 translates to Vout.
D1/D2 serve to stabilize IC1 by limiting the excursion of IC1 pin 6 from ground. I get why these diodes have a stabilizing effect, but I do not understand why it is necessary in this case.
Okay so that is about as much as I have understood about this circuit. Any insights from you professional EEs out there would be greatly appreciated, especially resources where I might be able to learn more about circuits specifically like this.
Edit to add: Thank you Andy Aka for bringing it to my attention that I forgot to include the Falstad circuit simulation that I set up. It did help me to understand more of the circuit but some things still eluded me, hence the post.