# DAC update rate vs ADC update rate?

I am building a system for ultrasonic distance measurement that implements CDMA coding access. Therefore, I am using DAC with 3 outputs for generation of three different signals and an ADC for reception. My final aim is to measure time of arrival.

DAC has 3 outputs, so for simultaneous transmission of three different signals I first need to load value to three registers and then to transmit them at the same time.

I have been trying to understand DAC80504EVM and ADS8920BEVM requirements and way of functioning. Can you somebody please support me whether or not the following is correct:

The datasheet for DAC specifies SPI clock speed of up to 50MHz. If I update the output values of DAC after 3 SPI transmissions, that would mean that I need at least 24x3 = 72 clock cycles in order to update my output. Therefore the update rate of DAC outputs would be 50MHz/72 = approx. 694 kHz. Or every 1/694 ms.

The datasheet for ADC specifies 1MSps sampling rate with 52MHz SPI clock speed. If I have both converters on the same SPI interface with the same clock of approx. 50MHz, it would mean that I would be getting 3x more data from the ADC. So for one sample value from DAC, I get three samples from the ADC.

Considering I would like to transmit signals with central frequency 300kHz and bandwidth 30kHz, would this actually be useful?

I understand that the DAC update rate is not its sampling rate, but I am still a bit confused with whether or not will the output of DAC be too slow for ADC, or does this make sense in terms of computing time of arrival?

I will appreciate any comment or suggestion.

• If 3 DACs and 1 ADC are on the same SPI bus then how are you interleaving them? Do you load all three DACs (72 cycles) then activate LDAC (instant) and then read the ADC (24 cycles) thus taking 96 clock cycles at 50 MHz = 520.8 kSps? What are your plans? Apr 15, 2020 at 12:59
• That was the idea, something like that. I am trying to understand would that work for the signal frequency that I want to use. That would not satisfy the Nyquist criteria for my 300 kHz signals. Right? Apr 15, 2020 at 13:03
• With my guess as to what you might do you would get a maximum centre frequency of 260.4 kHz (2 samples per cycle) and you would get two samples of your ADC tied in with that. That does not give you 300 kHz (as per what you want in your question) and it's even worse if you sampled your ADC more often so, it looks like you have a problem. Apr 15, 2020 at 13:20
• Maybe just use a separate data line for each chip? That should give you close to 2 MSps for each of them, placing the 300 kHz desired operation frequency easily within the first Nyquist zone. Apr 23, 2023 at 4:17

Suppose its time to get creative, you can actually read and write on an SPI interface at the exact same time.

You will need to write not 72, but 96 bits to load all 3 DACs, as the DAC's support daisy chain operation, this also means all 3 devices update at the exact same time

Equally the ADC will need to pull in 22 bits, so assuming there was no overlap, it would be 118 cycles per update / sample or about 424KSPS

So lets get crafty, not sure what your host device can do, but you could actually sample the ADC each time your writing to a DAC with a 100% overlap, assuming you don't actually need to read from the DACs, and can use some other external logic chip to interlock the ADC's SDI when you don't need to write to it,

This gets you to a cycle time of 96 cycles to update the output, and 32 cycles per ADC read. or a sample rate of 1.56MHz, there will be some lost time as you shuffle registers in the devices, but this should get you to your goal while making it a bit harder to configure the devices (something like an AND gate of a suitable frequency for the DAC output, and ADC input)

Edit: I will also add this is easiest if your SPI buffer is atleast 32 bits in size, and you may be able to DMA this as 2 way transfers are quite common in those peripherals.

• Do you think I need 96 bits for loading, because I would need 3 SPI transmissions for load register writings and one for LDAC activation? Apr 15, 2020 at 13:44
• Based on page 25 of the datasheet, you can only write to 1 register address at a time, and need to cycle the chip select between each write. ti.com/lit/ds/sbas871c/sbas871c.pdf Apr 15, 2020 at 13:50
• But I don't control CS through MOSI, don't I? I write to Dac0, then Dac1, then Dac2. With the CS cycling in between, and then I write to LDAC reg. Or I toggle it externally, via some of the GPIO pins on the DSP board? (The master is TMDSEVM6657 ti.com/tool/TMDSEVM6657). Please, don't feel bothered by my ignorance, I am trying to learn. Apr 15, 2020 at 13:57
• I'm not famiar with your device, but you control CS either via the SPI peripheral, or via code on the processor (some let you automate away some of it so that the selected CS is a different register, and writing to the SPI will automatically cycle that CS pin), so it would be CS low - write 32 bits - cs high save MISO as ADC result repeat for all 3 dac registers, with address bits and all. In reality you could use the little bit of helper logic to also tie the CS pins of ADC and DAC together at this time. Apr 15, 2020 at 14:02
• Then I would have 3x slower change of transmission signal then for the received one? For every sample from DAC I already get three samples from ADC? As I indicated in my post? But would the rate of change of DAC then be too slow, considering I wanna transmit 300kHz signals? Apr 15, 2020 at 14:09