I'm working on a school project where I have to interface an external ADC with a Digilent Nexys4 DDR board FPGA. The instructions are given in the following picture with a schematic of the simulation system. The schematic doesn't make sense to me. Would the nexys4 ddr board be the slave stimulus? Please explain with as much detail as you can what this schematic is trying to tell me.
The stuff on the left is what would be in your FPGA and the thing on the right simulates the ADC.
ADC Control State Machine would be the high-level logic sending commands to the ADC and receiving samples, etc.
TWICtl would convert a high-level representation of a TWI transaction into the actual low-level bit twiddling necessary for it. E.g. you would send TWICtl a single command to do a read, and it would then clock out all the individual control bits and and clock in all the individual response bits.