I need to design a 16 bit parallel data in and 32 bit parallel data out synchronous sequential glue logic circuit with output clock frequency half the input frequency.Can anyone please provide me an insight on its implementation..?
You can choose many design methods, timing diagram, state diagram, karnaugh mapping,
Consider starting like this.
then use counter bits for synchronous timing of the enable bits. If the output device is slow, and input device is faster in terms of delay time, then 1st two words could be writing on clock edges 1,2 leaving 3,4 for reading.