1
\$\begingroup\$

I need to design a 16 bit parallel data in and 32 bit parallel data out synchronous sequential glue logic circuit with output clock frequency half the input frequency.Can anyone please provide me an insight on its implementation..?

\$\endgroup\$
4
  • \$\begingroup\$ Whats the application? \$\endgroup\$ – geometrikal Nov 20 '12 at 12:37
  • \$\begingroup\$ I'd look into CPLDs for this kind of application \$\endgroup\$ – m.Alin Nov 20 '12 at 12:41
  • 7
    \$\begingroup\$ Smells like homework. Standard response: what have you tried so far? \$\endgroup\$ – Wouter van Ooijen Nov 20 '12 at 15:00
  • \$\begingroup\$ @ WOUTER VAN OOIJEN :This question was asked during my interview.I just have an idea that a delay element like flip flop or buffer can be used.It would be helpful if someone throws light on this. \$\endgroup\$ – Vidhya Nov 20 '12 at 18:42
1
\$\begingroup\$

From what you've said, all you need is 16 two-bit shift registers and a T-flip-flop.

enter image description here

You may want another stage of D flip-flops to slow down the transitions on the output data signals to the lower clock rate and to be sure they're syncronized to the new clock domain.

\$\endgroup\$
0
\$\begingroup\$

You can choose many design methods, timing diagram, state diagram, karnaugh mapping,

Consider starting like this. enter image description here

then use counter bits for synchronous timing of the enable bits. If the output device is slow, and input device is faster in terms of delay time, then 1st two words could be writing on clock edges 1,2 leaving 3,4 for reading.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.