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I have a wrapper, with multiple ports (mainly used to parameterize/scale a particular module) and in this wrapper i parameterize the module instantiation with help of generate for-loop. i.e.

generate 
for (genvar a=0; a< NUM1; a++) 
begin : module_label 
module module_inst( 
.x1(x1[a]), 
.x2(x2[a]), 
.x3(x3[a]), 
.y(y[a]) 
  );
end
endgenerate

Now i want to control my port connectivity inside this module instantiation based on some condition. Can i use a if loop within this instantiation? Something like :

generate 
for (genvar a=0; a< NUM1; a++)  
begin : module_label 
module module_inst( 
.x1(x1[a]), 
if ( NUM2 = 5) begin 
.x2(x2[a]), 
.x3(x3[a]), 
end 
.y(y[a]) 
);
end
endgenerate
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The ports on your submodule will always exist whether you use them on not.

If you don't connect an input/inout port of a submodule it will be connected to some default value by the synthesis tool. This is usually 'b0 for an input, or 'bz for an inout port, but could be anything. Leaving inputs unterminated is not ideal.

If you don't connect an output port of a submodule, it will be unused.

You don't however specify the definition of your submodule, so I have no idea what direction x2 and x3 are.


If x2 is an input, you can use a ternary operator such as:

.x2((NUM2 == 5) ? x2[a] : otherVal),

Where otherVal is whatever value you want to drive the port when NUM2 is not 5. This could for example be all bits as 0, or all z.


If x2 is an output, then you will want to move your if statement to outside the module instantiation:

if (NUM2 == 5) begin
    module module_inst( 
        .x1(x1[a]), 
        .x2(x2[a]), 
        .x3(x3[a]), 
        .y(y[a]) 
    );
end else begin
    module module_inst( 
        .x1(x1[a]),
        .y(y[a]) 
    );
end

That way you instantiate the module only connecting the outputs as required.


As a side note, your example code uses if(NUM2 = 5) which should read if(NUM2 == 5) - note the double equal for equality rather than assignment.

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