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I'm designing version 2 of a PCB. In the first version, I placed components as close together as possible to minimize board area (i.e. reduce board cost) and, for decoupling capacitors, to improve power supply decoupling performance. In practice this meant that the edge of a bypass cap pad would be about \$0.5\,\text{mm}\$ away from IC pin it decoupled (basically as close as I could get without violating the kicad courtyards). While I was able to do manual rework on these components, it wasn't all that fun. For rev2 I'm considering placing the caps a bit further away. Specifically, \$2\,\text{mm}\$ separation between decoupling caps and the IC, which is the diameter of the tip of my soldering iron.

As I see it, the downsides to this are:

  1. PCB cost for any additional board space used.
  2. Additional decoupling inductance, due to the longer connecting traces and therefore greater loop area.

Given the difference it will make, the first isn't a huge consideration since I won't mass-manufacture this board. For the second, I used this calculator to determine the additional inductance for \$2\,\text{mm}\$ extra distance and it was marginal (about \$0.56\,\text{nH}\$). I had a look at Electromagnetic Compatibility Engineering by Ott and in sec. 11.3 he mentions a good decoupling trace inductance as \$10\,\text{nH}\$ (for most onboard ICs mine should be significantly less than that). This leads me to believe the additional spacing is completely harmless.

There are of course benefits to keeping space around ICs. Obviously, easier hand-soldering/rework and also easier trace routing, to name just a few.

Have I neglected to mention any other downsides, or incorrectly represented the ones I did mention? My main concern is with the decoupling cap performance. Do other people do something similar for hand-assembled boards?

The PCB in question has noisy digital and noise-sensitive analog components. It's a radar operating at \$6\,\text{GHz}\$. It has an FPGA onboard driven by a \$40\,\text{MHz}\$ clock with fast edges (\$\approx 1\text{ns}\$) as well as a 12-bit ADC, a number of switching converters, an RF mixer, an RF LNA, etc. Given the mixed-signal and high-frequency nature of the board, my instinct is to do whatever I can to minimize noise, which includes proper bypassing. However, based on the calculation posted earlier the extra trace length seems insignificant.

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  • \$\begingroup\$ What's the highest analog signal bandwidth or the highest digital system clock frequency on the board? Is there any analog / video / RF? Is the digital side in the 200MHz clock range? If not, if it's something more like a 16MHz Arduino clone then the capacitor placement is more tolerant of additional parasitic trace inductance. Digital high/low transitions will not be as clean with the bypass farther away, but as long as the bandwidth is around 10-20x the maximum digital switching frequency, it should be acceptable. \$\endgroup\$ – MarkU Apr 17 at 0:31
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    \$\begingroup\$ It's actually a bit of a demanding PCB. There is a \$40\,\text{MHz}\$ clock on the PCB with fast edges (about \$1\,\text{ns}\$). There's an FPGA, a 12-bit ADC, a number of switching converters and then a bunch of RF circuitry for signals up to \$6\,\text{GHz}\$ (mixer, LNA, etc.). It's a radar if that gives you an idea. \$\endgroup\$ – MattHusz Apr 17 at 0:41
  • \$\begingroup\$ That makes me want to put the caps right next to the pins. But the calculations I did make it seem like it's not a huge concern. The second layer is very close to the first (6.7mil) so a cap a few mm away with a via to ground creates a pretty small lead inductance (unbroken ground plane connected to IC ground pins with another/multiple vias). I've read don't use vias for decoupling, but I don't really see why in this case. The additional inductance seems minimal. And the calculator I used said an additional 0.28nH/mm, which means the additional length is smaller L than what I get from the cap. \$\endgroup\$ – MattHusz Apr 17 at 0:46
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Seems like you've done due diligence in your reviews.

Maybe place the bypass capacitors at 2mm since simulation suggests it will be ok, but make sure the routing supports manual placement at 0.5mm. This might require scraping soldermask. If the prototypes show performance is impacted, you've got room to adjust and test.

At some point you run into limitations of what the models can predict, especially with RF and radar systems, and it becomes more economical to try it out on a prototype. (Obviously build and test a small prototype run before ramping up production.)

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  • \$\begingroup\$ I'm accepting this because I think this is sound and useful advice. However, I decided to play it safe and just place them as close to the pins they decouple as possible. \$\endgroup\$ – MattHusz Apr 21 at 5:32

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