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In an FPGA (Intel) design I have a PLL that is provided with a stable clock from a clock module on the PCB. The design is as shown on the figure below.

enter image description here

The PLL has a lock indication. After the FPGA is loaded, I have seen that the PLL gains lock in few milliseconds, and then has a stable clock output with high lock indication.

I have two questions:

  • Can the PLL lose the lock afterwards, so the design must be able to handle such loss-of-lock?
  • Are there any authoritative sources or documentation (like applications notes) that describe whether it is required to handle, or not handle, loss-of-lock in a simple design like the above?
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    \$\begingroup\$ The PLL won't loose lock as long as the input clock is stable, that the PLL is used within its normal operating conditions, etc... \$\endgroup\$
    – Grabul
    Commented Apr 17, 2020 at 13:11
  • \$\begingroup\$ @TEMLIB: Thanks for the quick reply, and that answer is surely along my expectations. However, we are discussing this in our design team, so to convince doubting souls, and have a firm base for decisions, I am also looking for some documentation to back this up. \$\endgroup\$
    – EquipDev
    Commented Apr 17, 2020 at 13:16
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    \$\begingroup\$ @EquipDev I'm not sure what other than what the datasheet promises you need. This is a case of "it's way more likely you have a bug than that the manufacturer of your parts has a bug". \$\endgroup\$ Commented Apr 17, 2020 at 13:23

2 Answers 2

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The PLL has a state machine (logic) as part of tracking phase and frequency.

If you trash the state transitions, or trash your "VCO" dividers, or trash your phase interpreter logic, you may lose lock.

So your team needs to understand the timing, to ensure any metastable operation is robustly handled.

Also you need to keeo the VDD clean and free of dropouts.

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If your "VCO" is not part of the FPGA (I assume this is an all-digital-PLL), then there is risk of some offchip transient event momentarily upsetting the VCO phase and frequency continuity.

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    \$\begingroup\$ I would agree that the biggest source of issues in PLLs is noise on the power rails which can cause phase noise within the PLL; I usually use an LC filter on the local rail to keep it really clean. \$\endgroup\$ Commented Apr 17, 2020 at 15:44
  • \$\begingroup\$ Thanks for the comment about power stability; so that is also something that must be ensure, just like having an stable running external clock. \$\endgroup\$
    – EquipDev
    Commented Apr 17, 2020 at 17:51
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Can the PLL lose the lock afterwards, so the design must be able to handle such loss-of-lock?

Some ways the PLL could lose lock:

  • The input clock signal is lost or changes frequency.

  • The RESET signal to the PLL is asserted for some reason.

  • The power supplies to the FPGA are unstable.

Are there any authoritative sources or documentation (like applications notes) that describe whether it is required to handle, or not handle, loss-of-lock in a simple design like the above?

There's no authoritative reference because it depends much more on the requirements of your particular application than on what any authority says.

Certainly there are many applications that might have to deal with an input clock signal that is only intermittently available, or that is switched between 2 or more sources.

And almost every FPGA design allows for a global RESET, even if it is only expected to be used during debugging.

On the other hand if you have unstable power supplies, that's probably something you should fix in the power supply design rather than try to handle within your RTL design. (For one thing because every other aspect of the FPGA behavior is probably also unstable in this case)

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  • \$\begingroup\$ Sure, reset and loss of external clock may/will result in loss-of-lock, so that must be ruled out; and stable power supply must also be ensured, as commented in the other answer. \$\endgroup\$
    – EquipDev
    Commented Apr 17, 2020 at 17:53

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