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Currently, I am using Logisim(yes, still Logisim) to build a 4-bit variant of the 8-bit SAP-1 microcomputer. However, I ran into a problem with the instruction register. Let me explain.

The SAP-1 has 5 instructions(LDA, ADD, SUB, OUT, HLT). These 5 instructions amount to 3 bits of data to read those RAM words. But that leaves only 1 bit for the address, and that means only 2 RAM addresses. To fix the problem, I tried to make the RAM words 6-bit instead(I don't know why I chose 6). But then I realized that having 6-bit RAM words would mean a 6-bit bus, and therefore a 6-bit CPU, which isn't good. Yet, 4-bit microprocessors carry on with upwards 40 instructions with kilobytes of memory. How do they do it, and how can I implement it into my 4-bit SAP-1?

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    \$\begingroup\$ just look at x86, 6502, z80, countless others...as answered variable instruction length, the term 4-bit or 8-bit or 32-bit doesnt necessarily have any limits on number of instructions, size of operations, address space, or other. Using the n-bit terminology is in general bad and creates more confusion than it solves. \$\endgroup\$ – old_timer Apr 17 at 15:13
  • \$\begingroup\$ Hm? I looked at the 4-bit Intel 4004 instrustion set and it had instructions that were 1 byte or more. Wouldn't 8-bit RAM addresses make the 4004 an 8-bit microprocessor, since those addresses have to go through the bus? \$\endgroup\$ – Trevor Mershon Apr 17 at 15:41
  • \$\begingroup\$ Again try not to get hung up on terms like "8-bit", "16-bit" and so on, because they have fuzzy definitions at best and really dont mean anything. They create more confusion than use. whatever the vendor called is what you call it there is no definition, if you see a definition in some dictionary or wikipedia, then it is wrong because the term is based on opintion, some folks think the deifnition is register size, some, address bus size, some data bus size, alu size and so on. \$\endgroup\$ – old_timer Apr 17 at 16:13
  • \$\begingroup\$ since it is rare for a processor to have all of those things the same size then you will generally have a strong difference of opinion on the term. x86 is an 8 bit instruction so do we call it an 8-bit processor? how many people call it that (other than maybe me). the 8088 was really a "16-bit" processor with an 8 bit external bus, but the thing was designed as a "16" bit processor, so do we call it that? it had a 20 bit address bus do we call it 20 bits, now it has 64 bit registers and a really wide data bus do we call it something else? \$\endgroup\$ – old_timer Apr 17 at 16:15
  • \$\begingroup\$ or just not bother with using terms that mean nothing useful and only cause problems. \$\endgroup\$ – old_timer Apr 17 at 16:16
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The SAP-1 has 5 instructions(LDA, ADD, SUB, OUT, HLT). These 5 instructions amount to 3 bits of data to read those RAM words. But that leaves only 1 bit for the address, and that means only 2 RAM addresses.

I think there are some serious misconceptions here. Being "4 bit" does not mean that your instructions are necessarily 4 bit, just as being 64 bit does not mean that your instructions are 64 bit. If you want to build a 4 bit CPU, you should look at what your CPU needs to do, and then pick an instruction size that makes sense for the application. Practical CPUs typically have either at least 16 bit instructions or a mechanism to make instructions variable length simply because a 4 bit instruction length doesn't let you do very much.

Yet, 4-bit microprocessors carry on with upwards 40 instructions with kilobytes of memory. How do they do it, and how can I implement it into my 4-bit SAP-1?

First, lets pick a common definition of what "4 bit" means. We'll say it means a system that has the general purpose integer registers all 4 bit. It doesn't mean that all registers are only 4 bit, but we'll assume the basic ones are. In that case, and with byte addressable memory, you would be limited to 16 bytes of RAM.

If you want more you have a few options:

  1. Make the address space larger, in which case you will probably need to make the registers larger, in which case you arguably no longer have a 4 bit processor
  2. Make the address space larger, but introduce a specific address register that is larger than the general purpose registers that can hold larger addresses (e.g. you have 4 bit integer registers and a special 16 bit register for memory pointers). Note that this may require you to be able to do ALU operations on greater than 4 bit values.
  3. Introduce a memory bank mechanism, where you have multiple 4 bit banks you can swap between, possibly by writing to a specific register, using a specific instruction, etc. This effectively just encodes memory addresses in two (or more) register values.
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variable-length instructions ---- suppose you want to jump with an offset of 550 from the current Program Counter? uses at least 3 of the 4-bit nibbles, just for the JumpOffset. Plus the opcode, which for Jump with Offset may need 2 more nibbles.

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  • \$\begingroup\$ Well, Jump with Offset isn't part of the instruction set. Is there a way to simplify it for a different instruction, like ADD or LDA? \$\endgroup\$ – Trevor Mershon Apr 17 at 15:26
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Also with the address problem, it doesn't mean that a 4 bit CPU can only handle 4 bit addresses, as an 8 bit CPU (like a Commodore 64 in the good old days) can also address 64 KB of memory which is 16 bits.

It just means, it cannot handle it at once, so first 8 bits are loaded, and than another 8 bits.

So if your CPU needs to handle 1 GB, it is still possible with 4 bits, but you need many of those to acquire the final complete address within the 1 GB.

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  • \$\begingroup\$ Alright, but this is the SAP-1, it is a very simplistic computer, is there a simpler way than fetching the memory twice? \$\endgroup\$ – Trevor Mershon Apr 17 at 15:24
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    \$\begingroup\$ If you need more bits than you can fetch in one go and you want to avoid multiple fetches.... try magic? (But first consider instruction prefixes, mode bits, multiple word instructions, different bit widths for code and data, etc.) \$\endgroup\$ – Wouter van Ooijen Apr 17 at 15:40
  • \$\begingroup\$ Alright, but variable machine cycles seem like they would require massive amounts of hardware to implement. \$\endgroup\$ – Trevor Mershon Apr 17 at 15:46
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    \$\begingroup\$ Maybe I could do bytes instead of nibbles for the RAM? It might work. \$\endgroup\$ – Trevor Mershon Apr 17 at 16:38
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    \$\begingroup\$ Then it's an 8-bit computer. \$\endgroup\$ – user253751 Jun 23 at 16:48

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