The SAP-1 has 5 instructions(LDA, ADD, SUB, OUT, HLT). These 5 instructions amount to 3 bits of data to read those RAM words. But that leaves only 1 bit for the address, and that means only 2 RAM addresses.
I think there are some serious misconceptions here. Being "4 bit" does not mean that your instructions are necessarily 4 bit, just as being 64 bit does not mean that your instructions are 64 bit. If you want to build a 4 bit CPU, you should look at what your CPU needs to do, and then pick an instruction size that makes sense for the application. Practical CPUs typically have either at least 16 bit instructions or a mechanism to make instructions variable length simply because a 4 bit instruction length doesn't let you do very much.
Yet, 4-bit microprocessors carry on with upwards 40 instructions with kilobytes of memory. How do they do it, and how can I implement it into my 4-bit SAP-1?
First, lets pick a common definition of what "4 bit" means. We'll say it means a system that has the general purpose integer registers all 4 bit. It doesn't mean that all registers are only 4 bit, but we'll assume the basic ones are. In that case, and with byte addressable memory, you would be limited to 16 bytes of RAM.
If you want more you have a few options:
- Make the address space larger, in which case you will probably need to make the registers larger, in which case you arguably no longer have a 4 bit processor
- Make the address space larger, but introduce a specific address register that is larger than the general purpose registers that can hold larger addresses (e.g. you have 4 bit integer registers and a special 16 bit register for memory pointers). Note that this may require you to be able to do ALU operations on greater than 4 bit values.
- Introduce a memory bank mechanism, where you have multiple 4 bit banks you can swap between, possibly by writing to a specific register, using a specific instruction, etc. This effectively just encodes memory addresses in two (or more) register values.