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This is a phase detector circuit used in PLL, the inverting input is a sinewave and there is a refernce signal which is a square wave

This is a phase detector circuit used in PLL, the inverting input is a sinewave and there is a reference signal which is a square wave. How would the output look like if the inputs are in phase and out of phase?

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The left op amp is acting as a switchable inverter, the sine wave input and output are in phase when the analog switch is open, and 180 degrees out of phase when closed

This is then fed to the right op amp which is an integrator this averages the ratio of time in and out of phase to an analog voltage to act as a feedback signal.

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This has the same transfer function as an EXOR gate. Having used an EXOR gate, back in university, to examine VCOs and phase_comparisons, I suggest you will have problems with lock_range and false locks.

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