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Is there a downside to using maximum possible VIAs (adhering to DRC rules) to connect two very long metals (ex. Power rails in Mx and Mx+1) running in parallel at block level? I know that multiple VIAs are preferred over a single via for current sensitive connections and that redundant VIAs increase reliability, but, is there something called excess VIAs?
I see a lot of you sharing their thoughts on PCB layout whereas I was looking for answer in an CMOS IC chip layout.
Excess would be the point where the board manufacturer replies saying it will cost extra to produce your PCB, as it costs them machine time drilling all those holes,
You can get pretty over the top with the number before they complain, (about 1200 on a 10x10cm 2 layer board from memory) avoid the minimum size, the smaller drill sizes break more frequently, and have a slower depth drilled per second which takes longer, so instead of a 0.3mm hole in your via, make it a 0.5mm hole and there will be much less friction, the larger the better if you don't need it tiny.
Other side effects on a circuit level is, well the hole is not as conductive as the trace, so you increase the resistance of any trace you shotgun spray with vias,
Other things can be a sort of tear along the dotted line problem, a rectangular PCB will normally curve when flexed evenly over the entire length, if you have rows of vias all in a line, that area will flex more than the rest of the PCB, and may be subjected to higher stress than the rest of the board,
Since you are asking about VLSI design rather than PCB design we don't have to talk about the cost of the vias.
However, in current VLSI manufacturing the horizontal distance between features on the same layer is comparable or less than the vertical distance between conducting layers. This means that sidewall capacitance to adjacent structures becomes significant. If you add many vias you are creating a large picket fence kind of structure, and there will be significant capacitance from the vias themselves to nearby wiring of other signals on the same metal layers. If there are not nearby signal wires then the fringing capacitance to the substrate will increase.
regarding n-silicon use of vias ---- in a linear setup of vias, clearly the vias eat up part of the metal width, thus reducing the current-carrying ability.
I suggest you use wide metal over wide metal, and have a line of vias down the middle of the metals, so the vias are fed with current from both sides and on each layer.
Summary: draw sketches of the current flows. A long thin metal overlap with lots of vias in a line will cause massive current crowding. Current crowding is NOT what you want.
There are usually rules regarding density in CMOS. Because modern CMOS processes use CMP between metalization layers, they need an even density of metal across the entire die. If your DRC rules do not contain any limit as to the maximum metal density, that is great. Usually you do require to have a certain minimum pattern of no-metal, but since large metal traces are allowed, I imagine you need a whole lot of vias before you have too many of them.
