How does one use a standard PHYS Ethernet controller? The datasheets do not give any schematics and mainly just give the pin descriptions.

I would like to serialize a TDM data stream, or a bit stream, through the Ethernet control to benefit from all of it's transmission methods rather than have to create these methods myself.

Since I want to stream the data as fast as possible I do not want to use packets. From the datasheets of a few PHYS Ethernet transceivers from TI they connect the inputs of the controller from a MAC and say use the term MII.

The best I can tell is that MII is a very minimum packet wrapper of the data. Does this mean I can't simply stream bits to the Ethernet control but must package them first?

Also, since I am bit dumping the data rather than using packets I need to tell the receiver in some way where the frame of data starts(it is repetitive) so it knows where "bit 0" is. I was going to use a separate TP for this but this seems like quite a waste. I think I use the 8b/10b to signal the first packet using one of the control words or something similar? But this assumes I can actually program this to the Ethernet controller?

This would be rather easy to do in FPGA as far as I can tell(I don't have a lot of experience with it though)? Would it be better to use an FPGA to encode the bit stream into 8b/10b and use control words to signal the start of the stream and still be able to get high speeds data transmission? (obviously still use differential signaling and magnetics like ethernet/RJ-45)

An FPGA would be suited ideally as a front end for my application and I imagine one could easily implement an ethernet controller on an FPGA. I do not want to implement a full controller though but simply use the FPGA to send data down TP or even FO. What are the draw backs to using an FPGA in this case to "emulate" an ethernet controller ignoring the "programming" issues(I assume one can probably download them)?

  • Are you wanting to send the data to a standard PC, or to another system you have full control over the hardware of? – Martin Thompson Nov 21 '12 at 11:17

Let's get some terms straight first: An Ethernet interface is typically made from two parts: a MAC and a PHY. The MAC, Media Access Controller, handles all of the packet assembly, transmission, reception, and error checking. A PHY handles all of the PHYsical transport stuff like modulating the signal, managing the DC balancing, tracking baseband wander, etc.

There are some things that both sides do, to some extent. Both MAC and PHY do some level of data error detection. This is not redundant error detection, but just error detection that is related directly to the types of things that the MAC and PHY do. Also, both MAC and PHY are dependent on the packet nature of Ethernet. The MAC because it is using the packet nature to filter, route, and manage the data. The PHY because there are certain signal modulation/demodulation functions that require packets (and the space between packets) to function correctly.

The point is: You cannot get away from packets even if you just use the PHY. Of course, the packet headers do not have to be "standard" headers. And the CRC does not have to be a standard CRC. But you are still limited to the maximum packet length and inter-packet-gap that standard Ethernet requires. (Note: You might be able to do "jumbo" packets if both PHYs support it.)

There are many benefits to using standard Ethernet packet headers, however. We would refer to this as a "Layer 2" protocol. The main benefit is that you can use standard Ethernet switches to help connect different devices together.

You mention just connecting a "TDM stream" directly (more or less) to the PHY. Every time someone has said that to me they have been talking about running multi-channel digital audio over Ethernet. If that is the case then you have a bunch of other issues, like clock synchronization and error detection that will prevent you from doing it the easy way. I won't cover audio over Ethernet more in this answer, but tell me if that is what you want to do because I can add a lot more info in that case.

Historically there have been many products that have taken some sort of data stream and ran it over Cat-5 using Ethernet PHYs and FPGAs, but without traditional MACs. Some of them have used the proper Ethernet Layer 2 or Layer 3 packets, and some of them have not. Some have also used non-Ethernet technology like ATM or FDDI. Some of them have used FPGA's, but inside the FPGA is a more traditional CPU and MAC.

I hope that at this point you have realized that what you want to do (use an FPGA and PHY to transfer a data stream over Cat-5) is difficult. Not impossible, but difficult. Let me try to explain how difficult.

First, you will have to master FPGA logic design. Of all the professional FPGA logic designers I know of, this project is beyond the ability of maybe 95% of them. These are people who have been designing FPGAs for several years or even several decades. It will take you a long time to learn FPGAs enough to design this logic. Probably years if you are doing this as a hobby.

Next, you need to learn exactly what a MAC and PHY do, and how they interface. This is not as hard as learning FPGAs, but it isn't easy either. There are a lot of basic concepts that are important, but not easily learned.

Now you'll have to design a PCB to do all of this. Designing a reliable PCB that uses FPGAs, PHYs, and does all of the proper Ethernet signal integrity stuff is also not easy. Not super hard either. But on a scale of 1-10, with 1 being super easy, this PCB would be about a 6. Not hard for an experienced professional, but definitely hard for a non-professional-EE.

At this point you probably noticed that I didn't directly answer your questions. This was on purpose. I could answer your questions, but honestly that wouldn't help you. It would be like telling you how to build the second story of a house when you haven't figured out how to build the first story or even the foundation.

Start by learning everything about designing FPGAs that you can. Also learn everything about Ethernet that you can. There are lots of online resources from app notes, datasheets, and how-to's. Go to opencores.org and study their Ethernet MAC cores. Do this diligently and in a year you might be ready. And when you are ready then you will likely know the answers to 75% of your questions-- and you will be able to put the other 25% into proper context so when someone does give you an answer it will actually be useful to you.

You can certainly use ethernet MAC+PHY to transmit any kind of data you want, mind you without having to worry about tcp/ip or udp stacks. The solution that leverages the most on existing ip and chips and is still very efficient would be to package your data in ethernet frames. Don't be afraid of this, the header is very simple and relatively low overhead, especially if you use jumbo frames, and the MAC module deals with the interface to the PHY (MII/GMII/RGMII), and things like CRC calculation.

You basically stream data to the MAC, and respect any wait requests you may get from it.

On the receive side (which is identical), the MAC streams to your app in the form of ethernet frames, again, very easy to decode. Usually the MAC has the option of discarding frames with wrong CRC.

Use gigabit ethernet for reasonably high speeds.

Simply put:

app(fpga) <-> MAC(fpga) <-> PHY(ext. chip) <-> Magnetics (ext. pkg) <-> connector

You don't have to write the MAC IP, so many have done it before, every major fpga vendor has an offering, and opencores.org has a free one (triple speed, tagged as stable).

You can start wih a dev kit before embarking in your own pcb, it will help you validate your design with minimum cost.

You could even start by validating the idea just with your computer by sending raw ethernet frames (google it, even Python provides an api for this), and later on this will help you verify what you are transmitting from the fpga.

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