0
\$\begingroup\$
module temp (

    input [1:0] A,
    output [1:0] O

);

    wire w0, w1;

    nand (w0, A[0], A[1]);
    nor (w1, A[0], A[1]);
    not (O[0], w0);
    not (O[1], w1);



endmodule

When I do an Analysis&Synthesis to above code, and then go for Tools->Netlist Viewers->RTL Viewer ;

I see the below one,

enter image description here

Now, the thing is, I have to implement a circuit with using NAND, NOR and NOT gates only, and there, I have an OR statement. So, I though I can do an OR out of NOR+NOT. But, as you see, the RTL viewer optimizes(?) my code and replaces NOR+NOT with an OR. Is there a way to prevent it doing so?

Thanks.


edit:

enter image description here

\$\endgroup\$
10
  • 1
    \$\begingroup\$ 'Hmmm' no more, friend. You're not in a large design and your assignment is about learning digital logic design. HDLs abstract you from the real circuit. You can churn out unreliable rubbish circuits that superficially appear to work. Understand digital logic design, don't just become a VHDL/Verilog writer. It's probably faster and easier on paper for a tiny circuit like this than in schematic capture, which I wouldn't use. They're trying to get you to understand the building blocks fluently. It's your choice but the goal isn't to find your personally comfortable path. \$\endgroup\$
    – TonyM
    Commented Apr 20, 2020 at 7:10
  • 1
    \$\begingroup\$ When I first learnt digital logic, I did all designs and mental simulations in sketches then schematic because there was no cheap HDL availability. When I moved to VHDL, I wanted to understand what logic circuits my VHDL would produce. The logic circuit is what we plug in and use, not the HDL. As I understood more and more of the logic produced by HDL, I could more directly in HDL - because I was well up that learning curve. You're right at the start and need to learn that. When designing a new circuit, as with my current FPGA, I picture or sketch out the important blocks before starting. \$\endgroup\$
    – TonyM
    Commented Jun 1, 2020 at 10:39
  • 1
    \$\begingroup\$ Getting the requirements and possible logic circuit right are the hard bit. Writing the VHDL is relatively easy. If you've got the first two right, you hit no problems in the HDL. You've worked out how to relieve tight timing, how to get the gate count down to what's required. The best logic circuit is the simplest: in nearly all cases it's the easiest to maintain, has fewest failure modes and is quickest to understand. (Comment HDL well, explaining 'why' something is, not what it is - your designs need to be easily maintainable by others, not by oneself from memory.) \$\endgroup\$
    – TonyM
    Commented Jun 1, 2020 at 10:48
  • 1
    \$\begingroup\$ @TonyM thanks for sharing your experience and thoughts. \$\endgroup\$
    – muyustan
    Commented Jun 1, 2020 at 10:51
  • 1
    \$\begingroup\$ Pleasure. Like all advice, take what's useful to you and ditch what isn't. Good luck and enjoy learning :-) \$\endgroup\$
    – TonyM
    Commented Jun 1, 2020 at 12:57

1 Answer 1

1
\$\begingroup\$

No, there isn't a way of stopping the gate reduction.

It's not optimisation, as it's an integral part of how Quartus interprets an HDL design and reduced to boolean equations during synthesis.

\$\endgroup\$
4
  • \$\begingroup\$ hmm, thank you for the answer. I will ask one additional question, if you don't mind. When I do a design for example in which the output of a NAND gate is directed to one of the inputs of an OR gate let's say. In RTL viewer, the name of the NAND gate is something like WideNand9 for example, so it knows it is a NAND gate. However, the bubbles are always at the other end of the cable, rather than right after the gate(AND) symbol. For my example, the buble is sticked to the input of the OR gate. Is this also something nonchangeable? \$\endgroup\$
    – muyustan
    Commented Apr 19, 2020 at 22:01
  • \$\begingroup\$ Do you mean the inversion bubbles are on gate inputs rather than gate outputs? Edit an example picture with text into your question. By the way, cables are insulated wires. These are just (virtual) wires :-) \$\endgroup\$
    – TonyM
    Commented Apr 20, 2020 at 7:14
  • \$\begingroup\$ ok, sorry for the word cable. It became a little bit unrelated with the original question, however, I added the picture. Now, all the gates at left are nand gates, I did not define them as nand keyword in verilog, however, they are the results of some ~& reduction operator. RTL viewer understands that they are nand gates, because it calls them WideNandx but, I don't understand why it moves those inversion bubbles apart from the gates. \$\endgroup\$
    – muyustan
    Commented Apr 20, 2020 at 10:09
  • 1
    \$\begingroup\$ Me neither but it does :-) \$\endgroup\$
    – TonyM
    Commented Jun 1, 2020 at 10:50

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