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I'm trying to implement this D flip-flop counter with + 1 logic through verilog. But I'm getting a lot of error codes about multiple contant drivers for net. Can anyone give me a hand im very new to this programming language. Here is also the code soo far

module LAB (clk, clear, Enable, Q);
  input clk, clear, Enable;   
  output[3:0] Q; 
  reg[3:0] Q;
  wire D;

  assign D = Q;

  always @ (posedge clk) begin
    if (!clear)
      Q <= 1'b0;
    else
      Q <= D;
  end

  always @ (Enable) begin
    if (Enable == 1)
      Q <= D + 1;
    else
      Q <= D;
  end 
endmodule

here are the error codes i am getting

Error (10028): Can't resolve multiple constant drivers for net "Q[3]" at
LAB.v(17) Error (10029): Constant driver at LAB.v(9)
Error (10028): Can't resolve multiple constant drivers for net "Q[2]" at LAB.v(17)
Error (10028): Can't resolve multiple constant drivers for net "Q1" at LAB.v(22)
Error (10028): Can't resolve multiple constant drivers for net "Q[0]" at LAB.v(22)
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 4 warnings
Error: Peak virtual memory: 4613 megabytes
Error: Processing ended: Sun Apr 19 18:39:09 2020
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
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  • \$\begingroup\$ Basically you can't set Q in two different always blocks. You have to figure out how to write one always block that handles both cases (Enable set or clear). \$\endgroup\$
    – The Photon
    Apr 19, 2020 at 19:24
  • \$\begingroup\$ I know it will work with using a single block but is there a way of using 2 blocks for this example \$\endgroup\$ Apr 19, 2020 at 19:26
  • \$\begingroup\$ No, using two blocks leads to the errors you found "Can't resolve multiple drivers". You can use an assign statement to represent the combinatorial logic, and an always block just for the flip-flops. But that would require introducing a new intermediate variable to hold the outputs of the combinatorial logic. \$\endgroup\$
    – The Photon
    Apr 19, 2020 at 19:28
  • \$\begingroup\$ what do you mean about this " But that would require introducing a new intermediate variable to hold the outputs of the combinatorial logic". So is it possible to use 2 always block when i introducing a new intermediate varible and if soo much more addtional code will be required ? \$\endgroup\$ Apr 19, 2020 at 19:32
  • \$\begingroup\$ Yes, it is, if you use an always @ * construct for that logic. See below. \$\endgroup\$ Apr 20, 2020 at 20:07

3 Answers 3

-1
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The error is caused by having two different always @ blocks assigning the same variable, Q. If you combine your logic into one always @ that error will go away. This is the normal way to solve the problem.

You have a number of other problems with your code, like your first always @. We'll fix this, but I want to think about the problem a little differently.

Say you don't want the combinatorial part of the logic in the main always @ block. You may want this to modularize the logic for example, or you may need to use some hardware macro. Whatever your reason, yes, that's possible. In fact there's at least 3 ways to do that.

First way: use a function:

module LAB (clk, clear, Enable, Q);
input clk, clear, Enable;
output reg [3:0] Q;

    always @ (posedge clk) begin
        if (~clear)
            Q <= 0;
        else
            Q <= incrementer_4 (Q, Enable);
    end

function incrementer_4;
input [3:0] a;
input increment;
    incrementer_4 = a + increment;
endfunction

endmodule

Second way: use an assign with an intermediate variable D:

module LAB (clk, clear, Enable, Q);
input clk, clear, Enable;
output reg [3:0] Q;
wire [3:0] D;

    assign D = Q + {3'b0,Enable};

    always @ (posedge clk) begin
        if (~clear)
            Q <= 0;
        else
            Q <= D;
    end

endmodule

Third way: create an async block using always @ with a wildcard sensitivity list, again with an intermediate variable:

module LAB (clk, clear, Enable, Q);
input clk, clear, Enable;
output reg [3:0] Q;
reg [3:0] D;

    always @ * begin
        D <= Q + {3'b0,Enable};
    end

    always @ (posedge clk) begin
        if (~clear)
            Q <= 0;
        else
            Q <= D;
    end

endmodule

So, yes, you can use two always @ statements, but not to the same variable.

All three of these examples will compile to the exact same result. The new concept I showed here is how to use the always @ * block to make async logic. It's not used often, but it comes in handy if for example a complex async logic element like case statement is needed.

I also introduced a couple of new syntax concepts:

  • vector fields {3'b0,Enable}
  • safer way of handling logicals (~clear)

Finally, I'm assuming your intent for the register is a synchronous reset. To make it async, you can add negedge clear to the register sensitivity list to make it behave that way.

More about always and the sensitivity list here: https://www.hdlworks.com/hdl_corner/verilog_ref/items/SensitivityList.htm

There's a fourth way, using a separate module and instancing that in your code. You would need to do this if, for example, you were using a library element and wanted to instance it explicitly.

And here it is:

module LAB (clk, clear, Enable, Q);
input clk, clear, Enable;
output reg [3:0] Q;
wire [3:0] D;

  increment_4 u_increment (Q, Enable, D);

    always @ (posedge clk) begin
        if (~clear)
            Q <= 0;
        else
            Q <= D;
    end

endmodule

module increment_4 (a, inc, sum);
input [3:0] a;
input inc;
output wire [3:0] sum;

    assign sum = a + inc;

endmodule
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  • \$\begingroup\$ dude you are amazing you saved soo much stress trying to make 2 always block to work \$\endgroup\$ Apr 21, 2020 at 22:21
  • \$\begingroup\$ Thanks. Tough crowd in this Q. \$\endgroup\$ Apr 21, 2020 at 22:24
  • \$\begingroup\$ Commonly speaking I know it would be easier whe combining both blocks which i know it works. My university professor was keen for us in using 2 always blocks with hardly and guidance on how to do so \$\endgroup\$ Apr 21, 2020 at 22:26
  • \$\begingroup\$ I never use always @ * unless I need to use a large case statement to make combinatorial logic. Maybe that’s what he or she is leading up to. Nevertheless, understanding the sensitivity list is key to using the always procedural. Sorry they’re making so much trouble for you! \$\endgroup\$ Apr 21, 2020 at 23:17
  • \$\begingroup\$ Dude i have another quesion, using the code for the always @ * can you implment s down counter from 9 to 0 whenever enable is 1 \$\endgroup\$ Apr 23, 2020 at 18:31
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The error messages are pretty clear. You can't assign values to the same variable in two different procedural blocks. You need to combine the two always blocks into a single block that is triggered by the clock.

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3
  • \$\begingroup\$ I know it will work with using a single block but is there a way of using 2 blocks for this example \$\endgroup\$ Apr 19, 2020 at 19:26
  • \$\begingroup\$ Well, OK then, have fun. \$\endgroup\$ Apr 19, 2020 at 19:36
  • \$\begingroup\$ -1 for not answering the Q, and for being kind of ass-y about it. \$\endgroup\$ Apr 20, 2020 at 20:04
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module LAB (clk, clear, Enable, Q);
  input clk, clear, Enable;   
  output[3:0] Q; 
  reg[3:0] Q;
  wire[3:0] D;

assign D = (Enable == 1) ? (Q + 1) : Q;

always @ (posedge clk or negedge clear) begin
    if(!clear) begin
        Q <= 0;
    end
    else begin
        Q <= D;
    end
end
endmodule
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