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I am learning logic circuit now.I am going to design a 4-bit binary counter with D-flip-flop.It counts from 0 to 15.And when the number reaches 15,the number wont change and remains 15.I am now working with the add function of the circuit,but I cant find where i get wrong.

This is the Truth Table I made. enter image description here

The Karnaugh Map and expressions of all D and CP enter image description here

Like you can see,when CP 1 activates Qa,CP2 gets activated due to (Qa !Qb),and CP3 gets activated then and CP4 got activated then.The result gets totally wrong!So can anyone points out my mistake?

Thanks in advance!

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1 Answer 1

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There is more than one way to make this device. There are synchronous and asynchronous counters.

We will take the simplest example: to make a clock (counter), we need to change the D-triggers into T-triggers. This is done by connecting \$\small\overline{\text Q} \$ to the \$\small {\text D}\$ input.

The Data Trigger works in the following way: if there is a 1 on its \$\small {\text D}\$ input and it receives a clock signal, the 1 from the \$\small {\text D}\$ input will be transfered to \$\small {\text Q}\$ and \$\small\overline {\text Q}\$ will become 0.

The table for \$\small {\text Q}\$ is as follows:

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

\$\small\overline {\text Q}\$ will always be the opposite of \$\small {\text Q}\$.

The left-most trigger is the least significant bit. The right-most trigger is the most significant bit.

After \$\small {\text Q}\$ changes to 0, the \$\small\overline {\text Q}\$ changes to 1, since \$\small\overline {\text Q}\$ is connected to the \$\small {\text D}\$ input on the trigger. On the next clock impulse, the 1 from the \$\small {\text D}\$ input will be moved to the \$\small {\text Q}\$ output, and so on for every trigger.

The circuit is here:

enter image description here

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