I figured a way to implement a fast divider (basically a ripple-carry divider) with deterministic delay, but it's stupidly-large, essentially requiring two AND gates (multiplier and a position test to line up the divisor and the dividend properly) and a full adder for half of n×n (to add the results of multiplication). It's essentially a combinational (i.e. unrolled) implementation of the below algorithm by Jain, Pancholi, Garg, and Saini:
In practice, the circuit would quickly grow so large as to have a relatively-high delay, so would be broken down into stages to avoid a low clock rate in e.g. a CPU or ALU. By pipelining the divider, you can put in one input per clock, and obtain a deterministic output with quotient and remainder once per clock; whereas if you're saving area, it wouldn't be pipelined, but would be a state machine and would remain busy until finished with the single division calculation several clock cycles later.
A single stage is two AND gates and a full adder for each bit of output, plus intermediate register to maintain state; a single asynchronous circuit has what amounts to ever-shorter horizontal ripple carry dividers at each stage feeding a vertical ripple-carry divider, so has the delay of e.g. a 64-bit ripple carry adder for 64x64 division. This doesn't seem to justify having what amounts to 64 ripple-carry adders running in parallel (at stage m, you need (n-m) full adders horizontally, and n-(n-m) full adders vertically).
The critical path would be 2 ripple-carry adders:
1 2 3 X X X X X C X X X X C C X X X C C C X X X X X X X X X X X X X X C X X X X X X X X X X X X X X X X X X X X X X X X X X X 4 5 6 7 C C C C X C C C C C C C C C C C C C C C C C X X C C C X C C C C C C C C X X X C X X C C X C C C X X X X X X C X X X X X 8 9 C C C C C C C C C C C C C C C C C C C C C C C C C C C C X C
It's still huge. Does anyone even use integer division? Is a combinational approach worthwhile, or is an iterative approach better for a general-purpose CPU?