An 8 bit value can range anything from 0 to 255 in decimal, or 00 to FF in hexadecimal. But why did they choose 8 bits for the byte, out of all of the powers of 2 they could have chosen? Even still, a nybble seems like a more suitable value for the smallest addressable memory unit, because it takes only one hexadecimal digit to write down. The main downside with nybbles though, is that they will require double the fetch cycles to execute properly. But in that case, why not just make the byte length equal to the word length, requiring only one fetch cycle per instruction? And if its so useful for a byte to be 8 bits, what is its use in microprocessors that aren't 8-bit? This could really help me out in designing my first Logisim CPU, so why are bytes 8 bits, and what is the use of an 8-bit value in non-8-bit computers?
Because basic transistor logic gates comes with two inputs and one output. When you cascade these logics, you get 4 inputs and two outputs, then you use the two outputs as two input for one final output. Each 2 input - one output operation is called a stage. At every stage, you multiply the bit processing by two. Each new bit multiplying the possible outcome by two, from the previous calculation. That's why the most rational efficient logic system will always be based on a stage multiple of two: 2 , 4, 8, 16, 32, 64 etc. Try to model a 3 input logic, it won't be as efficient as one bit will be often useless.
Why did they chose 8 instead of 4 or 16? Maybe because 4 was a bit short in information content and 16, a bit complicated to build in the early days.
\$\begingroup\$ What do you mean by cascading logic? I know about cascading amplifiers, but I have not heard about cascading logic. Could you please give me an example for cascading logic? \$\endgroup\$ Jan 5, 2021 at 5:25
1\$\begingroup\$ @Shashank V M By cascading logic, I mean when you use the output of two logic gates as inputs of a third logic gate. \$\endgroup\$– FredledJan 12, 2021 at 18:35
\$\begingroup\$ Thank you, I am able to understand now. \$\endgroup\$ Jan 13, 2021 at 14:12
Your question has a lot of hidden assumptions about CPU architecture.
A study of the way ancient computers were designed can reveal quite a bit about why such choices are made today.
As to why there are 8 bits in a byte comes down to technical inertia and good enough. It wasn't always like this and in the future binary as a basis for digital computing may be as out of date as vacuum tubes and electromechanical step relays are today.
Sixty years ago electromechanical was the leading edge because everything else was too unreliable. The Fujitsu FACOM 128, one is still operational, uses 5 bits as a byte to represent one decimal digit. The Digital Equipment Corp. PDP8 has a 12 bit word and does not use 8-bit bytes at all. 8-bits per byte became a de-facto standard with the IBM System 360. Because it was IBM it was easier to make yours compatible than to risk being shutout of government contracts like UNIVAC or Burroughs by not working like the IBM.
Many architectures are implemented with multiple data paths within the CPU so that the source and destination objects can be accessed at the same instant.
One of the most popular (cheapest) controller architectures is the Microchip PIC family. They have different number of bits for instruction words, ALU data, and call stacks.
So 8-bits per byte and using the same memory for program and data storage is the least complex way to implement a CPU that yields "good enough" performance. It does this by making the fewest possible interconnects between the elements of the CPU.
Retrocomputing has a good history: https://retrocomputing.stackexchange.com/questions/7937/last-computer-not-to-use-octets-8-bit-bytes
As you have already spotted, non-power-of-two word sizes are a bit awkward. That puts paid to the 36-bit systems. Baudot code is also awkward at 5 bits, and doesn't have enough characters to represent both upper and lower case. ASCII standardised at 7 bits; EBCDIC (by IBM) at 8. 7 bit ASCII rounds up to 8, and using 8 bits gives enough room for some letters from non-US alphabets.
So, why not larger?
It should be noted that some systems effectively do have a larger minimum addressable unit: ARM and other RISC architectures has strong alignment requirements. You can't fetch a word from an odd address.
The "octet" is now thoroughly embedded in all sorts of standards, so if you want to make a machine with a larger minimum addressable unit your code will end up having to unpack words to bytes a lot.
\$\begingroup\$ Interesting situation of the DEC Alpha : retrocomputing.stackexchange.com/questions/13920/… \$\endgroup\$– TEMLIBApr 20, 2020 at 22:07
\$\begingroup\$ @TEMLIB They made the decision to not support "lane changes." DEC Alpha was probably the purest RISC design I've ever encountered. (And I worked with the original MIPS R2000 and Dr. Hennessey "back in the day.") If you really want to scream your brain out, have a look at how it handled instruction execution exceptions! \$\endgroup\$– jonkApr 21, 2020 at 4:21
In modern machines, 8 bits satisfies two basic requirements:
- Enough bits to hold a Latin upper- and lowercase alphabet (e.g. ASCII and EBCDIC)
- power of 2 for efficient addressing
Nevertheless there were earlier machines (like the one I learnt FORTRAN on, the DECSystem-10) that used 6-bit characters and shortened character coding. Many of these 1960s-era mainframes were 36 bits (like that DEC-10), which is a big enough word for large-ish floating point numbers.
Why did they do this? Memory and datapath hardware were very, very expensive back in the 1960s and early 70s, so saving bits helped keep the machine costs down. 6-bit characters were good enough for FORTRAN and COBOL, who would need more, right?
As the 1960s drew to a close, the advent of lower-cost transistors, integrated circuits and semiconductor memories made scrambling for bits become less important, while machine elegance and software development costs became more important. 8-bit ASCII was introduced in 1969, in anticipation of the inevitable change coming to the computing landscape. Likewise, the surviving manufacturers moved on to 8-bit and power-of-two wordlengths (like the 16-bit DEC PDP-11 and 32-bit VAX) and consigned 6-bit characters to history.
Not to be ignored, IBM's early adoption of 8-bit characters, first with S/360 in 1964, left competitive makers playing catch-up.
More about all that here: https://www.eetimes.com/how-it-was-ascii-ebcdic-iso-and-unicode
That said, it is possible to create a machine of any wordlength if it is used for a special purpose. 48 bits is common for DSP work for example, and 4-bit microcomputers still exist.
\$\begingroup\$ How many bits was ENIAC? I just looked it up and it says it stores 10-digit numbers but I don't know what types of digits those are. Because if that's decimal, it's frankly mind boggling on top of how ENIAC was built and if it's binary, it's still a lot higher than what I thought it would be considering how its construction. \$\endgroup\$– DKNguyenApr 20, 2020 at 20:52
\$\begingroup\$ So bytes are 8 bits because that's all you really need for text characters? That seems like far from the only use for them when Paul Malvino's Digital Computer Electronics references them before referencing ASCII, if at all(I havent gotten through the book yet, but its a good book). \$\endgroup\$ Apr 20, 2020 at 20:57
\$\begingroup\$ I also just read that the Pioneer 10 did not use the Intel 4004 because it was "too new". So what did it use?!! \$\endgroup\$– DKNguyenApr 20, 2020 at 21:05
1\$\begingroup\$ According to this, it used TTL chips. cpushack.com/space-craft-cpu.html \$\endgroup\$ Apr 20, 2020 at 21:22
1\$\begingroup\$ @DKNguyen: Eniac was decimal. It used a 10 count ring counter for each digit. 36 tubes per digit. \$\endgroup\$– JREApr 20, 2020 at 21:32
My super hand-wavey made-up reason is because n = 8 is the minimum number that results in \$2^n\$ having at most 1% step size, (i.e. the minimum required to usefully represent information and measurements in the real world) where n itself also a power of 2 so address space is not wasted.
The next step down for n results in \$2^2\$ = 16. Handling math and measurements for real-world applications leaves something to be desired when you only have 16 steps with which to represent things.
n = 7 also gets you at most 1% step size for fewer bits but seven doesn't satisy \$2^n\$ so you end up with address capacity that gets wasted (i.e. To uniquely identify each of the 7 bits you need to use 3 address bits anyways, but 3 address bits can identify \$2^3 = 8\$ bits so if you use 7-bits you're not making full use of those 3 address bits.)
I have no idea how much water this holds though.
The OP's question kind of implies the decision was made by committee. But reading around, starting at the Intel 4004, it seems more likely that what happened was the number of bits kept increasing until 8 was reached and it happened to serve most purposes well for the amount of hardware required and so it stuck around for a long time and thus became the standard.
But why did they...Who’s they? Also you mentioned to 00 to FF being one byte of data. This is true. It’s commonly used for serial communications. Why it’s not just 0 to F is beyond me. Perhaps they just wanted more possible outcomes. \$\endgroup\$