I have some doubts about the systematic offset problem of an op amp. Here (slide 15) it is quite well explained:

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Briefly, it is due to the fact that Q6 and Q7 may not be crossed by the same current. But there are two things that I do not understand:

1) I have also been told that the offset is due to the mismatch of the main transistors of the differential pair. Is this mismatch linked to the current mismatch of Q6 and Q7 shown by the previous slide?

2) How is it possible that Q6 and Q7 are crossed by different DC currents? The load is assumed to be an infinite impedance and the only path between Q6 and Q7 goes across a capacitor Cc, which is an open circuit at DC.

In my university course I have also used this schematic for an op - amp:

enter image description here

This schematic is similar to that shown in the initial slide, with the difference that now there is a third stage which is a voltage amplifier. Let's zoom on the second stage (which is the cause of the systematic offset):

enter image description here

The current that flows in M7 and M12 is the same: and it is obvious because there are not other paths for DC current! But there is a small DC offset in output (116uV) when DC input values are 0.

This seems to be in contrast with the definition of systematic voltage given in the previous slide.

  • \$\begingroup\$ Initially you are talking about input offset voltage and, in the end you are looking at output offset voltage of an open-loop op-amp. That doesn't seem logical. \$\endgroup\$
    – Andy aka
    Apr 21, 2020 at 12:25

1 Answer 1


I think you should make a distinction between what I would call "balance" and "offset".

In my view your circuit actually doesn't have any Offset! All transistors are all perfectly matched and identical, or exactly 10 times wider if W is 10 times larger for example.

Offset is a statistical effect that is the result of small variations between transistors (and other components). You usually simulate this using a Monte Carlo simulation and for that also statistical models are required.

Balance is the result of the circuit, for example making sure that the input differential pair transistors (M1 and M2) are identical in size and have a identical operating points meaning the same \$I_D\$ but also the voltage must be the same. If that is the case (and it looks like it is in your circuit, at least in the input stage), your circuit is balanced.

The 2nd and 3rd stages in your opamp both add a very large amount of gain (I would never do that, chances are this opamp will be unstable when feedback is added) because these stages are all "current into a high impedance point" amplifiers. So even the smallest imbalance is amplified a lot. Even small numerical rounding off of the simulator could show up this way. My guess is that the 116 uV you see is caused by this.

I would just ignore that 116 uV and consider it to be zero. Also I would suggest to limit the number of "current into a high impedance point" amplifier stages you have now as these WILL get you into trouble. That's my 25 years of design experience tip :-)


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