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Bus capacitance limits number of devices that can be connected by I2C. What problem is encountered if one tries to exceed this limit can anyone explain this in detail please.

Thank you

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What is bus capacitance in I2C?

It's the same as any capacitance - consider the copper traces running over a ground plane. There is some capacitance between the metal, determined by the total area of the traces and dialectic constant between them. Devices on the bus will also have some known capacitance between their IO pins and ground. I2C bus signals can be in the range of 100kbit/s, 400kbit/s or even 1Mbit/s. Adding a capacitor to ground on these signal lines will increase the rise and fall times of the I2C signal lines.

How does it limit the number of devices on the bus?

Each additional devices adds input capacitance to the signal lines in addition to increasing the bus trace area on the pcb. There's also additional noise added due to the longer traces. As the capacitance on the outputs increases, the signal lines become more sloped. If it's too high, they won't ever reach the threshold for any slave devices on the bus to recognize the signal at all. Or, in the case of the data line, the value might not reach the threshold in time to be registered.

Electrical Theory

Consider what an I2C connection looks like in a device. The SDA and SCL lines are said to be "Open Drain" which means they are connected to ground through an N channel FET and can sink current. Therefore, they can pull the lines low, but not set them high. That's why you need to connect external pullup resistors to the control lines. The lines are monitored through a diode which has some input threshold which must be overcome.

schematic

simulate this circuit – Schematic created using CircuitLab

So pulling the signal low is very quick, but to go high, current must flow through the external resistor and the internal circuitry to ground. This is not instantaneous, and any additional capacitance on the lines will further increase the rise time.

Here are some example waveforms of a 50kHz clock line. The actual capacitor values are just to prove the point.

sck clock waveform

Practical Considerations

The device input capacitance is typically around 10pF, but exact values can be found in the datasheet. Another value to consider is the maximum sink current of any of the open drain connections, as this will put a lower limit on the pullup resistor values.

This technical article from All About Circuits does an excellent job at visualizing these concepts and digging deeper into the calculations for signal rise time and acceptable pullup values.

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    \$\begingroup\$ Thank you for making me understand it @Kurt E. Clothier \$\endgroup\$ – Amrathesh Apr 22 at 4:10
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You need at least 2 time constants of risetime, given the passive pullup. Otherwise the positive-going waveform will not reach a clean "high" and the data-sampling circuits will conclude a "0" was transmitted.

Thus for 1Kohm pullup and 500 pF total capacitane (wiring, PCB, the ICs hanging on the buss with ESD protection and their data-sampling circuits), you have 500 nanoseconds time constant, and since you need at least 2 tau settling (with that being quite marginal), the bittime must be at least as long as 2 * 500nS = 1,000nS = 1uS => 1MHz rate.

I imagine Philipps has conservative specs on their IP. Respect that.

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    \$\begingroup\$ Many i2c devices have maximum sink current specifications of 2-3 mA so 1kohm would be too low in a 5v system. The lowest acceptable would be 2.2k. \$\endgroup\$ – Kevin White Apr 21 at 16:00
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    \$\begingroup\$ The NXP spec only requires 3mA of sink current in standard mode and fast mode, @KevinWhite makes a valid point. The specified maximum bus load for these two modes is not 500pF, it is 400pF. \$\endgroup\$ – Elliot Alderson Apr 21 at 16:18

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