How to generate fast clock signal with MAX10 and PLL?

Question

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal.

I'm using the following code to test if the clock signal generated is correct, by manually setting the v1 variable so my led blink every second. In this example the PLL (generated by the ALTPLL wizard from the Quartus IP Catalog) is set to receive a 100MHz clock signal and should display a 400MHz clock signal however nothing happens.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

LIBRARY altera_mf;
USE altera_mf.all;

--   debut entity     --

entity test is 
    port(
        CLK : in std_logic;
        LED0 : out std_logic     -- leds are ON for '0' and OFF for '1'
    );
end test;


-- debut architecture --

architecture test_led of test is 
signal s_led0 : std_logic :='1';
signal c0 : std_logic;

component pll400
    port(   inclk0      : IN STD_LOGIC  := '0';
            c0      : OUT STD_LOGIC 
    );
end component;

begin

clk1:pll400
    port map(inclk0 => CLK, 
                c0 => c0
    );

p:process(c0,s_led0)
variable v1 : integer range 0 to 800000000 :=0;
begin               
    if c0'event and c0 = '1' then
        v1 := v1 + 1;       
        if v1 = 400000000 then
            s_led0 <='0';   
        end if; 
        if v1 = 800000000 then
            s_led0 <='1';
            v1 := 0;
        end if;
    end if;

LED0 <= s_led0;
end process;    
end test_led;

I was able to use this to generate and test signal up to 320MHz , but it doesn't seem to be able to go higher, though I found in the datasheet that the VCO was able to go up to 1300MHz (I noticed that the Pfd limit is 325MHz, is that linked ?).

So is there something I'm missing or is it impossible to generate such signal with my current board ?

Edit : datasheet I am using as references : MAX10 Clocking and PLL 10M50 User Guide MAX10 Datasheet

Edit2 : I removed this post from stackoverflow to post here, where it is more suitable.

Edit : Here is a schematic of the PLL, right now i have access to the parameters N, M and K, but I can't change the post-scale C counter, located just before the output. Given the comments and answers I had, it should be what I need to stay in range of both VCO and PFD and still getting the desired output frequency (>400MHz)