I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal.

I'm using the following code to test if the clock signal generated is correct, by manually setting the v1 variable so my led blink every second. In this example the PLL (generated by the ALTPLL wizard from the Quartus IP Catalog) is set to receive a 100MHz clock signal and should display a 400MHz clock signal however nothing happens.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

LIBRARY altera_mf;
USE altera_mf.all;

--   debut entity     --

entity test is 
        CLK : in std_logic;
        LED0 : out std_logic     -- leds are ON for '0' and OFF for '1'
end test;

-- debut architecture --

architecture test_led of test is 
signal s_led0 : std_logic :='1';
signal c0 : std_logic;

component pll400
    port(   inclk0      : IN STD_LOGIC  := '0';
            c0      : OUT STD_LOGIC 
end component;


    port map(inclk0 => CLK, 
                c0 => c0

variable v1 : integer range 0 to 800000000 :=0;
    if c0'event and c0 = '1' then
        v1 := v1 + 1;       
        if v1 = 400000000 then
            s_led0 <='0';   
        end if; 
        if v1 = 800000000 then
            s_led0 <='1';
            v1 := 0;
        end if;
    end if;

LED0 <= s_led0;
end process;    
end test_led;

I was able to use this to generate and test signal up to 320MHz , but it doesn't seem to be able to go higher, though I found in the datasheet that the VCO was able to go up to 1300MHz (I noticed that the Pfd limit is 325MHz, is that linked ?).

So is there something I'm missing or is it impossible to generate such signal with my current board ?

Edit : datasheet I am using as references : MAX10 Clocking and PLL 10M50 User Guide MAX10 Datasheet

Edit2 : I removed this post from stackoverflow to post here, where it is more suitable.

Edit : Here is a schematic of the PLL, right now i have access to the parameters N, M and K, but I can't change the post-scale C counter, located just before the output. Given the comments and answers I had, it should be what I need to stay in range of both VCO and PFD and still getting the desired output frequency (>400MHz) PLL schematic


If you can divide down the input clock frequency inside the device then you can operate at (say) 200 MHz internally (easily suiting the PFD) whilst having the VCO output running at 400 MHz. I don't know if the PLL has this internal facility or not but, given that the data sheet says it can operate at frequencies (Fin) up to 472.5 MHz it would be pointless if it can't be divided by 2 to obtain a frequency that is within the operating range of the PFD (phase-frequency detector).

You need to do some digging around and hopefully you'll find that a programmable divider sits between Fin and the PFD ready for you to program to divide-by-two. If you find it you might need to juggle some other numbers because now, internally, you will be needing to compare with a 200 MHz clock.

  • \$\begingroup\$ Hi, thanks you for your answer. After some digging I was able to modify most of the parameters of the PLL, but there is still one that I can't access and I believe it would be the key to make it work. Right now I have acces to M and N (range 1 to 512) such as VCO = Fin * M/N, and a post-scale counter K (1, 2) that divide VCO before reinjecting it into the PFD. The last parameter, post-scale counter C, ranged between 1 and 512, is nowhere to be found in the .vhd of the pll, do you have any idea where I could modify it ? It could allow me to stay in range of both PFD and VCO. Thanks a lot. \$\endgroup\$ – KilianW Apr 27 '20 at 14:07
  • \$\begingroup\$ I am unfamiliar with the specifics of the device but I do have reasonable enough general knowledge about PLLs in FPGAs to have made the answer. \$\endgroup\$ – Andy aka Apr 27 '20 at 14:13

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