Clock generation on FPGA pin

Question

I am trying to interface an FPGA to a DAC device. The DAC has a JESD204B interface so the data clock is embedded in the serial data lane (it uses the 8B/10B encoding).

The DAC still needs a clock input, CLK, (LVDS) to drive the DAC sample rate clock. It can actually be a lower clock rate as the DAC has an internal clock multiplier. I think the lowest clock rate I am required to achieve would be about 65 MHz. Obvious the FPGA needs the same root clock to generate the samples at the same/correct rate.

I am trying to decide if I can simply use an FPGA pin to generate this 65 MHz clock. I'm generally not sure if this is a good idea or not (would jitter be particularly bad?). Also, I'm not sure what is the best method to achieve this. Do FPGAs have internal constructs specific to generating clocks on output pins, would I utilizes a simple DDR output block, or would it be best to consume a SERDES or GTX?

I guess the alternative is to use an external clock synthesis chip. Two output clocks can be generated, and one is sent to the FPGA for DAC sample production, and the other is sent to the DAC for sample consumption. I don't think the phase relationship between the two is critical.

Answer 1

One way or another your FPGA will need some kind of reference clock to work. The DAC performance will of course be influenced by the quality of its own clock.

If you use a good, low-jitter reference, the FPGA can make very good clocks using its internal PLL synthesizer block (verify this with your specific FPGA.)

However, if carefully-controlled clock spectrum is paramount (and it can be for some RF applications), you can use an external clock synth that has the spectral profile your DAC needs to achieve its performance. Choose a synth with two outputs: one for the FPGA, and one for the DAC. TI makes some good ones.