I've heard that a typical graphics card uses around 100 A of current and only 1 V of voltage. Is there a specific reason why not to use the other way around, so high voltage and low amp? Usually high current leads to high losses, that's why power transmission lines usually prefer high voltage instead of high current. So what am I fundamentally not understanding why that is a bad idea for integrated circuits?

  • 1
    \$\begingroup\$ IC's dont split a high voltage into smaller voltages with more current - that's an AC thing for power lines. (yes, i know, buck/boost converters exist, im talking purely about AC power lines here). each transistor needs a small voltage but the many transistors need that current. See my answer (now edited) for a more indepth explanation \$\endgroup\$
    – QuickishFM
    Commented Apr 21, 2020 at 18:32
  • 1
    \$\begingroup\$ Most IC's are low voltage and low current. It is true that some power hungry high speed digital IC's use very high current. I guess your question is, could those high current IC's be designed differently so that they use high voltage and low current? \$\endgroup\$
    – user57037
    Commented Apr 21, 2020 at 18:42
  • 3
    \$\begingroup\$ @mkeith Not particularly. I just picked a graphics card as an example because I thought that all ICs followed the same logic. Turns out that I'm wrong. So your suggestions would be a kind of follow up question, but not what I initially wanted to know. Thank you for the sugestion. \$\endgroup\$
    – Maxim
    Commented Apr 21, 2020 at 18:48
  • 1
    \$\begingroup\$ @Maxim Modern digital ICs use CMOS gates. CMOS gates are a bit special - they don't behave like traditional resistors (your description of current loss). CMOS gates use zero (almost zero as to be effectively zero) current when idle. They only consume current when they switch state (from on to off or off to on). As such, the current used by graphics cards is a function of MHz/GHz and if you increase the voltage you WILL use roughly the same current thus increase Watts - to decrease Watts you reduce the voltage from 5V to 3.3V to around 1V \$\endgroup\$
    – slebetman
    Commented Apr 23, 2020 at 4:40
  • 1
    \$\begingroup\$ @Sean I'd far rather touch a 5V connection that supplies 10kA, than a 10kV 5A one. The volts determines the actual current that will flow through the body (and at 5V, that's almost none). You can have a power-line at 200kV with zero current flowing, but it's still lethal. \$\endgroup\$
    – SusanW
    Commented Apr 26, 2020 at 17:02

7 Answers 7


I am not sure why this wasn't the first thing pointed out by any of the earlier answers, but it is because as transistors are made smaller to increase speed, increase density, and reduce power consumption, the gate oxide layer is made thinner (which also increases leakage currents).

A thin gate oxide layer can't withstand very high voltages so you end up with a device that only operates at very low voltages. Thin oxide layers also have more leakage so you don't want a high voltage anyways since that would just increase leakage current and increases static power consumption.

Your mistake is this:

Data processing, unlike power systems, isn't about power delivery; It's about data processing. So it is not that designers choose to operate at low voltages and high currents thus going against \$I^2R\$. Yes, they are concerned about power consumption and heat due to losses, but they aren't concerned with the efficient delivery of power. A power designer has to deliver X amount of power and would increase voltage so they could decrease current while delivering that same power. A digital designer would outright decrease the "power output" if they could.

Their optimizations necessitate low operating voltages which results in high leakage currents. The goal of these optimizations is to allow smaller transistors so you can pack more of them in as well as switch them faster, and when you have millions upon millions of transistors switching very frequently that results a lot of charging/discharging the gate capacitances. This dynamic current results in the high peak currents which can be tens of amps in high-speed, high density digital logic. You can see that all this current and power is undesired and unintentional.

Ideally, we would like really no current at all because our concern is information, not energy/power. High voltages would also be nice for noise immunity but this runs directly counter to making transistors smaller.

  • 12
    \$\begingroup\$ Further reading: Modern Microprocessors A 90-Minute Guide! has some discussion of the fact that higher frequency typically requires more voltage to push charge around faster. But at higher voltage, that's more charge for the same gate capacitance, so power scales with V^2 at constant frequency. And increasing frequency means pushing the same charge around more often. So assuming you run at minimal V for any f, power scales with f^3 as you increase frequency and voltage to make it work. The "power wall" is the limit of power density \$\endgroup\$ Commented Apr 22, 2020 at 4:34
  • 5
    \$\begingroup\$ (The part that scales with f is the dynamic power from charging and discharging the tiny capacitance. When most transistors are flipping, dynamic power tends to dominate, but leakage current is significant for stuff like large caches, or execution units that are often idle. en.wikipedia.org/wiki/Dark_silicon - power gating is important for modern CPUs) \$\endgroup\$ Commented Apr 22, 2020 at 4:39
  • 1
    \$\begingroup\$ Your point about information processing is a good one. Especially since heat is thermodynamically created in a processor when memory is erased. If it takes more energy to activate a cluster or transistors that comprise a bit of memory, that much more energy is pushed back out as heat. \$\endgroup\$
    – nomen
    Commented Apr 22, 2020 at 16:02

The power required to switch a capacitance from logic 0 to logic 1 (or vice versa) is proportional to the clock frequency times the supply voltage squared. In CMOS digital circuits the logic gate inputs look like capacitors, so charging and discharging capacitances uses most of the power in these circuits.

As you mention, the \$I^2R\$ losses in conductors will go up, so the low voltage power supplies are placed as close as possible to the processor. Look at a modern motherboard and you will see a 12V connector very close to the CPU. You will also see several large inductors and capacitors...these are for the low voltage switching power supplies.


In addition to Elliot's point about the power required to charge the tiny capacitances associated with each transistor in a GPU or high performance CPU. consider the size of each transistor.

In the early 1980s people didn't worry much about electrostatic protection, but I started paying attention when I first came across a transistor with a 1 micron gate insulation width (in 1982). It's electric field strength (volts/metre), not just voltage, that causes high voltage breakdown.

You can get a lot of V/m across a micron.

Now, minimum feature sizes are a couple of orders of magnitude smaller, so connecting the tiny transistors in a CPU's core logic to the traditional 5V supply would simply destroy them.

I/O transistors were built outsize and especially tough, and chips used separate supply rails for the I/O interconnections. But increasingly, even these can only tolerate 3.3V, or even down to 1.8V. In FPGAs, pretty much only trailing edge devices are still 5V tolerant.


My answer is similar to DKNguyen's excellent one, but I'll phrase it differently.

First, in an integrated circuit, voltage and current are independent. Ideally, you want both to be as low as possible. But as always in engineering, there are design conflicts that force you to make tradeoffs.

So let's look at voltage and current separately.


There are some points to be made for using a high(er) voltage, and some for a lower voltage. The original TTL logic (such as most of the chips used in the 1977 Apple ][ computer outside the CPU itself) ran at 5 volts. TTL logic is still ubiquitous; you can still buy most of the same chips Steve Wozniak used in the 1970s. In landline phone systems, the dial pulses (which really are just digital bits if you think about it) used as much as 48V.

Today, you go down as low as 1 Volt.

Pros for high voltage

Reliability. If you have a poor-quality circuit (such as a 7-mile thin copper telephone wire), it's much easier to reliably tell the difference between 48V and 0, but darn near impossible to tell apart 1V from 0V. Basically high voltage "just works" no matter what.

That's pretty much it. In today's highly integrated circuits, which are really extreme precision instruments, and with 50+ years of manufacturing experience to achieve this precision, you don't need that kind of ruggedness, so lower voltages work just as well.

Edit: as Peter Cordes pointed out, higher voltage does have a second advantage; it can allow increased speed because the voltage reaches the threshold of reliable detection quicker. I hope I paraphrased that correctly.

Pros for a low voltage

  • Low energy consumption, which translates to longer battery life and less heat output. Edit: Peter Cordes pointed out that lower power consumption also translates to the chip simply not melting. That's a very real problem. Some CPUs will actually explode in a matter of a few seconds if you forget to put on a heat sink.
  • Higher speed. There simply are fewer electrons to shuffle around (although that technically depends on the charge rather than the voltage, these two are linked in practical terms).
  • You can use thinner insulators without having to worry about current breaking through. That translates to thinner insulators. Exception: floating-gate transistors are actually designed for current breaking through an insulator. That's why writing and erasing flash memory takes a high voltage.

So when you are talking about a computer circuit, low voltage clearly wins.


Now let's look at current. As DKNguyen already pointed out, designers also want to keep the current as low as possible, in part to reduce heat, and in part to extend battery life in smartphones etc.

But to understand what's going on, you really shouldn't be looking at the 100A, or whatever it is. That might be an average, or more likely is an average when there is heavy graphics load.

If your graphics card was perfectly inactive (which it never is, not even close!), the current would actually be close to 0A. The transistors in microchips are (somewhat simplistically speaking) usually arranged as CMOS transistor pairs in series, where always one is in "on" mode and the other in "off" mode. So current can never flow, in theory. In practice, when the transistors switch, for a very short time, there usually is a very short period (measured in picoseconds) when both are "on" - basically, a short circuit. This switching happens billions of times per second (depending on the GPU's clock frequency, mostly), and in anything from a few thousand to millions of transistors at the same time, depending on how active your GPU is. So your 100A is actually not constant 100A, but a series of nearly 0A, followed by extremely short spikes of potentially even a lot more than 100A.

Edit: Peter Cordes also pointed out that the 0A is an idealization in the first place. There is a lot of parasitic current leaking through the transistors, as well as pretty much everywhere on the chip.

There is a second issue with current. A lot of components (such as the bits in dynamic RAM) in a chip act as capacitors (they are actually transistors wired as capacitors). Writing 0s or 1s into such capacitors means storing or removing electrons from the capacitors. The higher the current (and the smaller the charge), the less time that takes. Edit: as Peter Cordes pointed out, besides the capacitors in the circuit intentionally, there also is a lot of additional capacitance all over the place (for instance from components or wiring being just adjacent), which also contributes to the same problem.

To reduce current, designers have a few options:

  • Reduce speed. That reduces the number of switching operations (and therefore current spikes), and also allows charging or discharging the capacitors at a lower rate.
  • Turn off parts of the circuitry that isn't used right now. Again, that is done during sleep mode.
  • Reduce the time when both transistors in a pair are "on" so the spikes are shorter.
  • Lower the voltage. According to Ohm's law, lower voltages translate to lower currents.

The first two are mostly done in sleep mode, and also when a computer starts to overheat. Infamously, Apple also at one point slowed down their iPhones to reduce current consumption when the batteries started to get old.


You also mentioned high losses in power lines (where voltages are high and currents are low). That's a very different situation. In a computer, the losses are always 100%; nearly all electricity is converted to heat (except for a few that are converted to light, radio energy for WiFi or the like).

So the goal isn't to reduce losses, but to reduce the total power.

  • 2
    \$\begingroup\$ For a given gate capacitance, higher voltage overall lets you run faster (at the cost of more power: power scales with V^2 from pushing more charge around, and having more energy per charge). That's why over-clockers raise the voltage on CPUs, and why regular DVFS idle vs. turbo raises voltage along with frequency (en.wikipedia.org/wiki/Dynamic_voltage_scaling). If you're running at just barely enough voltage for logic to even work, it takes longer for next gate's input to stabilize at a "definitely on" state, increasing gate delay. This applies when we're talking 1.2 vs. 1.1V, not 48 \$\endgroup\$ Commented Apr 23, 2020 at 11:44
  • 2
    \$\begingroup\$ So the benefit to low voltage is that it makes high speed possible without melting. As lighterra.com/papers/modernmicroprocessors explains, power density became the obstacle in around the pentium-4 era, putting a ceiling on CPU frequency gains and ruining Intel's plans for a very high frequency but deeply pipelined CPU. \$\endgroup\$ Commented Apr 23, 2020 at 11:47
  • 2
    \$\begingroup\$ close to 0A - only with power gating of idle parts. Tiny transistors have significant leakage current in the "off" state. The smaller the feature size, the worse the problem, so static power becomes more of an issue compared to dynamic power. (Dynamic power will usually dominate, though.) Also, there's a typo in there: you wrote 0V once. But overall good answer, going into details about relevant factors. \$\endgroup\$ Commented Apr 23, 2020 at 11:50
  • 2
    \$\begingroup\$ A lot of components (such as the bits in dynamic RAM) in a chip act as capacitors - My understanding is that parasitic and gate capacitance is actually where most of the (dynamic) current consumption in CMOS logic goes. Not just DRAM which is designed to have some capacitance. Perhaps that's what you meant by "a lot of components", but maybe it would be better to be clear that most of the capacitance is parasitic, not designed in on purpose. \$\endgroup\$ Commented Apr 23, 2020 at 11:56

The many transistors in an IC are connected to the VCC and ground lines, not to each other - so they won't be "sharing" voltages so to speak like they would in series (which doesnt make sense for CMOS as it relies on restoring logic of current passing from a strong VCC source, not daisy chained through some million transistors).

CMOS blocks are all connected to the same VCC so they'll take more current with the same voltage - as if they were in parallel. Because the transistors need only 1V to work, you only need 1V. But, there are billions of transistors - and you need to source current to every single one of them. Thats why you have a hefty power supply and decoupling capacitors to source the 100A or so current in times of need (long story short the power lines can act as an inductor and when the billion transistors switch on at the same time, they need a HUGE rush of current - decoupling capacitors provide this when the wire is still opposing the huge current rush).

Thats why you need a lot of current but a small voltage.


To add about the power transmission lines, it is true that the lower current results in lower loss but these are AC lines and you can use a transformer to convert it to a lower voltage with a higher current (i.e. when the power lines get to a town and the houses need 230V and not a few kilovolts). That is a fairly different concept here, as IC's use DC only. I believe your underlying question was regarding the use of high current in ICs and not necessarily the IC's capability of converting between high/low voltage and current. I can definitely understand your confusion between the topics however - I hope my answer explained it.


I will give you my answer which is based on digital logic 101 which I took many years ago. Power loss in a clocked integrated circuit is given by this formula:

P = V^2 * C * F

Where P is power, C is the capacitance, V is the voltage (VCC) and F is the clock frequency.

This is why power hungry chips are optimized to minimize VCC. If they used a higher V they would consume even more power.

Note that C is the process capacitance for the transistor level geometry and type of fabrication used.

In particular the MOSFET gate layer may be made extremely thin in low voltage IC's. However, this also increases capacitance, C. So there are trade-offs. But since the power is proportional to V^2 it is usually worthwhile to minimize V.

  • 1
    \$\begingroup\$ Technically this is only one component of the power. This is called the dynamic power or switching power. There is also leakage power because the gate insulation layer is not perfect, and some current flows through it even when the clock is stopped. \$\endgroup\$
    – user57037
    Commented Apr 21, 2020 at 18:55
  1. Higher voltage breaks transistors.

Modern transistors are tiny, and cannot withstand high voltage. The smaller we make them, the lower the voltage has to be, to prevent electrons from jumping between traces and destroying the device. Historically it was 5V, then went down to ~1V in current equipment. Think wire insulation - wires rated for 10k volt have vastly thicker coat than wires you find in toys.

  1. Transistors use a lot of current (amps) because there is a lot of them. Expect 10 bilion in modern device (1 000 000 000).

Other answers dig into details as to why is that.

  1. Power efficiency

As you noted yourself, it would be beneficial to send 1A at 100V than to send 100A at 1V.
In fact, manufacturers already do this!

CPU and video cards often have a dedicated 12V connectors, and only convert to ~1V right before it goes into processor. You can see array of capacitors and converters around the processor (rounds and box pieces, often with own heatsink). You would be surprised how much current flows there (100 of ampere) and how many processor 'legs' are dedicated solely for powering it.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.