I have a differential ADC (HX710) that I am using to interface a load cell. The wiring is as follows with (J4) going to the load cell: enter image description here

Mostly, this reads very reliably and accurately. However, intermittently the ADC reading will stick at a seemingly arbitrary range of values (ie. not a power of 2) that would normally represent a very high weight (but not a max reading with respect to the ADC's range). I can't consistently get the circuit into this state. It seems almost random - say every 20th power cycle?

During this failure mode, I can completely unplug the load cell from the system and the ADC will still be floating in this high range.

Under normal circumstances, running the ADC without a load cell returns just the expected unweighted value bouncing around in the noise floor.

Is there a reason that a differential amplifier, like this, might get stuck in a high range intermittently?

  • \$\begingroup\$ Does it latch for minutes on end disconnected? Also, check if shorting pins 3 and 4 makes it go away. Are there decoupling caps? \$\endgroup\$
    – DKNguyen
    Commented Apr 22, 2020 at 1:51
  • \$\begingroup\$ Does the failure mode start as soon as the device is powered up (5% chance), and continue until the device is unpowered? That could point towards a power sequencing issue somewhere in the system. \$\endgroup\$
    – MarkU
    Commented Apr 22, 2020 at 2:40
  • \$\begingroup\$ @DKNguyen good point, shorting pins 3 and 4 does not change the reading as it does when the ADC is functioning as excepted. \$\endgroup\$ Commented Apr 22, 2020 at 2:49
  • \$\begingroup\$ @MarkU the failure isn't necessarily always right on power up. Sometimes it will drop into this state during normal function. \$\endgroup\$ Commented Apr 22, 2020 at 2:50
  • \$\begingroup\$ What is driving LoadCellEnable? \$\endgroup\$
    – crj11
    Commented Apr 22, 2020 at 3:13

1 Answer 1


This ended up being a software problem. The HX710 has two modes: A) differential input B) DVDD-AVDD measurement. You set the mode for the next conversion period by the amount of PD_SCK trailing pulses in the current conversion period. This is shown on page 5 of the datasheet:

datasheet screen shot

In the driver code, I neglected to disable interrupts during the data clock out period. This was the cause of the intermittent failures. It seems that interrupting during the clock out sequence would sometimes cause the ADC to begin reading out DVDD-AVDD instead of the differential input. That explains why I would see it hang at an arbitrary value not responding to any inputs from the load cell.

Disable global interrupts while driving time sensitive peripherals!

Lesson learned.


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