To design a PCIe*8 carrier board for a XC7K160T module, what is the requirement for the PCB?
The 16 pairs are all adjacent to each other on the 0.6mm pitch B2B connector of the module with ~20mm span , the signals on the card edge span ~40mm. The module is planed to be placed as close to the PCIe connector as possible. But *8 still means some horizontal routing and vertical spaces for routing.
For example the vertical space is 20mm, then all signals are in a (20-40mm)*20mm area, then trace length on the carrier board won't be longer than 40mm, suppose the signal rise time is 100ps, then the trace length is several times the rise length, then impedance should matter even on this small area, and I'm not sure whether will this be a "work by luck" design with such many connections (chip to module to carrier to motherboard to chipsets).
It is said PCIe3.0 works on FR4 but is at the upper limit of FR4 https://www.intel.com/content/dam/doc/guide/pci-express3-phy-implementation-considerations-idf2009-presentation.pdf, even 10GT/s's eye won't open well.
FR4 also may have many grades, what is the requirement and what to tell the PCB manufacture?
The carrier board is very simple, can very low cost 4 layer board from small vendors be used (can they even replace FR4 with some lower grade material)?